HDL17_MIPS CPU Design using Verilog.pptx

Verilog design

1. MIPS CPU Design using Verilog Tsung-Chu Huang Dept. of Electronics Eng., National Changhua University of Education, Taiwan 2023/1/5

2. Outline Introduction to MIPS32: ISA & SPIM Instruction Formats Addressing Modes Instruction Set Architecture and Assembly Language Compiled by SPIM Single-Stage MIPS Design Program Counter (PC) Instruction Memory (IM) Register Files (RF) Arithmetic Logic Unit (ALU) Data Memory (DM) 5-Stage Pipeline MIPS Design Basic Pipeline Design by Spatial Gate-Level Design Explanation for Term Project 2

3. Introduction to MIPS Famous Microprocessors CISC: 4004: ’71 Intel. First CPU  8008  8080  80x86 (applied in PC) 6502 (#T) : Motorola (applied in Apple II)  68000  68030 (applied in Sun Workstations) RISC: MIPS (Mega Inst. per Sec): ’81, Prof. Hennessy, Stanford U.  ’92 MIPS Co.  ’18 Wave Comp. ARM (Advanced RISC Machine): ’83 Acorn Co.  ’90 ARM Co.  ’16 SoftBank RISC-V: ’10 UCB Open Project  ’15 Foundation MIPS MIPS Co. converted to develop RISC-V, but MIPS is still popular in CPU Design course/lecture due to its concise pipeline stages. 32 32-bit Registers: argument: $a0 ~$ a7 = $0~$7 save: $s0 ~$s7 = $8~$15 temp: $t0 ~$ t9 = $16~$23 value: $v0 ~$v7 = $24~$31 (returned value ) $28=$ gp (global pointer ), $29=$ sp (stack pointer ), $30=$ fp (frame pointer ), $31=$ ra (return address) 4GB Mem, 32-bit Word, 30-bit absolute address (therefore, only 2-bit J), State Control 3

4. Instruction Formats 4 Destination Source Target   Shift Amount

5. MIPS Register Files (RF) 32 Registers Pseudo Instructions in Assemblers 5 Register Num b er Register Name Des c r ip t ion $ze r o T he v alue 2 -3 $ v - $ v 1 ( v a l u e s ) f r o m expre ss i on e v a l u a t i o n a n d f u n c t i on res ul ts 4 -7 $a - $ a3 ( a rg u m e n ts) Fir s t f o u r p a ra m et e rs f or s u b ro u t i ne 8-1 5 , 2 4- 25 $t0 - $t9 T e m p o ra r y v ar i a b l es 16 - 23 $s - $ s7 S a v ed v a l u es re p rese n t i n g f i n a l co m p u ted res u l ts 31 $ r a R et u rn a d d ress Di r e c ti v e Result .word w1, ..., wn S tore n 3 2 -b i t v a l u es i n suc c es s i v e m e m o r y words .half h1, ..., hn S tore n 1 6 -b i t v a l u es i n suc c es s i v e m e m o r y words .byte b1, ..., bn S tore n 8 - b i t v a l u e s i n suc c es s i v e m e m ory w ords .ascii str S tore the A S CII str i ng str i n m e m o r y . S tr i n gs are i n d o u b l e - q u o tes , i .e. " Co m p u ter S c i e n ce " .asciiz str S tore the A S CII str i ng str i n m e m o r y a n d n u l l -ter m i n a te i t S tr i n gs are i n d o u b l e - q u o tes , i .e. " Co m p u ter S c i e n ce " .space n L e a v e an e m p t y n - b y t e re gi on of m e m ory f or l at e r use .align n A l i gn the n e x t d a tum on a 2 ^ n b y te b o u n d a r y . For e x a m p l e, .al i g n 2 al i g n s t h e n e x t v alue on a w ord b o u n d a r y

6. MIPS Instruction Set Arithmetic Logical 6 Inst r uction E x a m p l e M e a ning add add $1,$2,$3 $ 1 = $ 2 + $3 subt r a c t sub $1,$2,$3 $ 1 = $ 2 - $3 add immedia t e addi $1,$2,100 $ 1 = $ 2 + 1 add u n signed addu $1,$2,$3 $ 1 = $ 2 + $3 subt r a c t u n signed subu $1,$2,$3 $ 1 = $ 2 - $3 add immedia t e unsigned addiu $ 1,$2,100 $ 1 = $ 2 + 1 M ultiply ( w ithout o v e r flo w ) mul $1,$2,$3 $ 1 = $ 2 * $3 M ultiply mult $2,$3 $ hi , $l o w = $ 2 * $3 Di v ide div $2,$3 $ hi , $l o w = $ 2 / $3 Inst r uction E x a m p l e M e a ning and and $1,$2,$3 $ 1 = $ 2 & $3 or or $1,$2,$3 $ 1 = $ 2 | $3 and immedia t e andi $1,$2,100 $ 1 = $ 2 & 1 or immed i ate or $1,$2,100 $ 1 = $ 2 | 1 shift l e ft logic a l sll $1,$2,10 $ 1 = $ 2 < < 10 shift r ig h t logic a l srl $1,$2,10 $ 1 = $ 2 > > 10

7. MIPS Instruction Set Data Transfer Conditional Branch 7 Inst r uction E x a m p l e M e a ning load w o r d lw $1,100($2) $ 1 = M e m o r y [ $ 2 + 1 ] st o r e w o r d sw $1,100($2) M e m o r y [ $ 2+1 0]=$1 load u p per immediate lui $1,100 $ 1 = 1 0x 2 ^16 load add r e ss la $1,label $ 1 = A d dre s s of l ab el load immed i ate li $1,100 $ 1 = 1 m ov e from hi m fhi $2 $ 2 = hi m ov e from lo m flo $2 $ 2 = l o m ov e m ove $1, $2 $ 1 = $2 Inst r uction E x a m p l e M e a ning b r anch on equ a l beq $1 ,$2,100 i f ($ 1 = = $ 2 ) g o t o P C + 4+1 b r anch on n o t equal bne $ 1,$2,100 i f ($ 1 ! = $ 2 ) go to P C + 4+1 b r anch on g r e a t e r than bgt $ 1,$2,100 i f ($ 1> $ 2 ) go t o P C + 4+1 b r anch on g r e a t e r than or equal bge $ 1,$2,100 i f ($ 1 > = $ 2 ) g o t o P C + 4+1 b r anch on l e ss than blt $ 1,$2,100 i f ($ 1 < $ 2 ) go t o P C + 4+1 b r anch on l e ss than o r equal ble $ 1,$2,100 i f ($ 1 < = $ 2 ) g o t o P C + 4+1

8. MIPS Instruction Set Comparison Jump 8 Inst r uction E x a m p l e M e a ning s e t on l e s s than slt $1,$2,$3 i f ($ 2 < $ 3 ) $ 1 = 1; e l s e $ 1=0 s e t on l e s s than immediate slti $1,$2,100 i f ($ 2 < 1 0)$ 1 = 1; e l s e $ 1=0 Inst r uction E x a m p l e M e a ning jump j 1000 go to a d dre s s 1 jump r egis t er jr $1 go to a d dre s s stored in $ 1 jump and link jal 1000 $ra = P C + 4; go t o a d dre s s 1

9. System Calls in SPIM 9 S e r v i c e Ope r ation Code ( in $ v 0) A r guments Results p r in t _int P r i nt i n te g er nu m b e r (32 b i t ) 1 $ a = i nt e g e r t o b e pri n t e d None p r in t _float P r i nt f l o a t i ng- p oint n u m b e r (32 bit) 2 $ f 12 = f l o at to be pri n t e d None p r in t _double P r i nt f l o a t i ng- p oint n u m b e r (64 bit) 3 $ f 12 = d o u b l e to be pri n t e d None p r in t _ s t r ing P r i nt n u ll - t er m i n a ted ch a ra c ter s tr i ng 4 $ a = a d d ress of s tr i ng i n m e m o r y None r e a d _ int Read i n t e g er n u m b e r f r o m user 5 None In t e g er ret u rn e d i n $ v r e a d_fl o at Read f l o ating- p o i n t n u m b e r f r o m user 6 None F l o a t ret u rn e d i n $ f r e a d_doub l e Read d o u ble f l o a t i ng -p o i nt n u m b e r f r o m user 7 None Dou b l e ret u rn e d i n $ f r e a d _ string W o r k s t h e sa m e a s S ta n da rd C L i bra r y fgets() f u n c t i o n . 8 $ a = m e m o r y a d dre s s of str i ng i n p ut b u f f er $ a 1 = l e n gth of str i ng b u ff er ( n) None sbrk Ret u rns t h e a d d ress to a bl ock o f m e m o r y co n t a i ning n a d d i t i o n a l b y tes. (U s e f ul f or d y n a m i c m e m o r y a l l ocatio n ) 9 $ a = a m o u nt a d dre s s i n $ v exit S top program f r o m ru n n i ng 10 None None p r in t _ c h a r P r i nt ch a racter 11 $ a = ch a rac t er to be pri n t e d None r e a d _ char Read c h ara c ter f rom user 12 None Char ret u rn e d i n $ v e x it2 S to p s program f r o m ru n n i n g a n d returns an i nt e g e r 17 $ a = res u l t ( i nt e g er n u m b e r) None

10. SPIM – Assembler of MIPS Install QtSPIM from Cloud/Lab16, or + glibc for MIPS 10 > File > Load > Hello.asm

11. Modular (Gate-Level) Design Program Counter (PC) Instruction Memory (IM) Register Files (RF) Sign Extension Unit (SE) Arithmetic Logical Unit (ALU) Data Memory (DM) 11

12. Program Counter 12 + PC 4 + b ranch <<< 2 1

13. Instruction Memory (IM) 13 IM Address Instruction 32 32

14. Register Files (RF) 14 RF Read Data2 32 Read Reg1 5 5 32 Read Data1 32 Read Reg2 Write Reg Write Data 5

15. Sign Extension 15 16-bit branch x 4 = 32-bit offset address  

16. ALU 16 ALU ALU_result 32 Zero scr1 32 scr2 32 4 ALUop 5 shamt

17. Data Memory (DM) 17 D M Write Data Read Data 32 32 Address 32 R/W

18. Controller 18 CU

19. Single-Stage Generic MIPS32 19 Write Clk + PC 4 + 1 IM RF ALU D M   CU

20. 5-Stages Pipeline MIPS 20 PC 4 IM   RF + D M ALU 1 1 + IF (Instr. Fetch) ID (Instr. Decoder) EX (Execution) MEM (Memory) WB (Write Back) IF_ID ID_EX EX_M M_WB

21. R-type Instructions with no confliction with others 21 PC 4 IM   RF + D M ALU 1 1 + IF (Instr. Fetch) ID (Instr. Decoder) EX (Execution) MEM (Memory) WB (Write Back) IF_ID ID_EX EX_M M_WB

22. lw (Load Word) 22 PC 4 IM   RF + D M ALU 1 1 + IF (Instr. Fetch) ID (Instr. Decoder) EX (Execution) MEM (Memory) WB (Write Back) IF_ID ID_EX EX_M M_WB

23. sw (Store Word) 23 PC 4 IM   RF + D M ALU 1 1 + IF (Instr. Fetch) ID (Instr. Decoder) EX (Execution) MEM (Memory) WB (Write Back) IF_ID ID_EX EX_M M_WB

24. Branch Instructions 24 PC 4 IM   RF + D M ALU 1 1 + IF (Instr. Fetch) ID (Instr. Decoder) EX (Execution) MEM (Memory) WB (Write Back) IF_ID ID_EX EX_M M_WB

25. Time-Space Diagram 25 i1 i2 i3 i4 i5 i4 i3 i3 i2 i2 i2 i1 i1 i1 i1 PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 T ime Space (Simple MIPS without consideration of hazards  stall  forwarding)

26. RR-WR Read-Write (Forward) Dependency  OK 26 RR WR i3 i4 i5 i4 i3 i3 WR WR WR RR RR RR RR PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 T ime Space (Simple MIPS without consideration of hazards  stall  forwarding)

27. WR-RR Write-Read (Backward) Dependency  STALL 27 WR RR i3 i4 i5 i4 i3 i3 RR RR RR WR WR WR PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 PC IM   RF + D M ALU 1 1 + 4 T ime Space (Simple MIPS without consideration of hazards  stall  forwarding) Read an old value

28. Exercise & Lab16 (Install gcc with MIPS library –march=mips2 ) (Write a program using C and compile to MIPS Assembly) Install SPIM Write an Assembly program ( eg . Fibonacci.s ) using SPIM Simulation in SPIM and prepare source codes and golden data. Design a partial MIPS CPU using Verilog Write a testbench ( testfixture ) for Golden Test Simulation using ModelSim (Modified several instructions for I/O in DE0/Cyclone III) (Demo reduced MIPS using DE0/Cyclone III FPGA) 28

29. Term Project Based on Lab16, demo and explain your MIPS by any of the following efforts: Adding one or two instructions from a full MIPS and execute an assembly program with the additional instructions. Install glibc / gcc and compile a C program to MIPS assembly code and then simulate them and explain. Hints: Windows > cmd DOS > powershell PS > SWL --install PS > SWL SWL > sudo apt install gcc - mips - linux -gnu g++- mips - linux -gnu SWL > gcc - mips - linux -gnu -O3 -S -mfp32 -march=R2000 hello.c Using Compiler Explorer at https:// godbolt.org / Adding I/O and demo on the DE0/Cyclone III. EDA scripts for connecting the SPIM to MIPS Simulations Any improvement that you deserve a bonus. 29