Here's a comparison table between Simulation-Based Verification and Formal Verification. I'll also add it to your presentation.

gOOD

1. Mid-Semester Presentation SystemVerilog Assertions, Formal Verification, JasperGold App, and Scheduling Semantics

2. Introduction • Importance of Verification in Chip Design • Overview of Topics: SVA, Formal Verification, JasperGold, Scheduling Semantics

3. SystemVerilog Assertions (SVA) • Purpose: Checks properties of signals • Immediate vs Concurrent Assertions

4. Immediate Assertions • Syntax: assert (expression) else $fatal("Assertion Failed!"); • Use in combinational logic checks

5. Concurrent Assertions • Example: property p1; @(posedge clk) req |=> ack; endproperty assert property (p1);

6. SVA Operators • Boolean: and, or, not • Sequence: ##, |->, |=> • Property: strong, weak

7. Advantages of SVA • Improved Debugging • Reduced Simulation Time • Enhanced Verification Coverage

8. What is Formal Verification? • Uses mathematical proofs • Exhaustively checks all possible states

9. Formal Verification Techniques • Model Checking • Equivalence Checking • Theorem Proving

10. Formal Verification vs Simulation • Simulation tests specific cases • Formal Verification explores all corner cases

11. Advantages & Disadvantages of Formal Verification • Advantages: No need for testbench, detects deep corner cases • Disadvantages: Computationally intensive, complex

12. JasperGold App • AutoFormal: Automated checks • QuickCheck: Fast bug detection • Proof Strategies: Guided formal verification

13. JasperGold Workflow • Steps: 1. Load Design 2. Define Properties 3. Run Formal Verification 4. Analyze Results

14. SystemVerilog Scheduling Semantics • Understanding Simulation Event Regions • Impact on Assertions Execution

15. Scheduling Conflicts & Race Conditions • Potential Issues: Non-deterministic behavior • Best practices for race-free design

16. Project Implementation • Assertions and Formal Checks Applied • Challenges and Solutions

17. Results and Observations • Success Metrics and Improvements • Comparison with Traditional Simulation

18. Conclusion • Key Learnings: SVA, Formal Verification, JasperGold • Future Work

19. Thank You! • Closing Statement • Contact Information