IC PROCESSING

unit 5 of IC Technology RTU 8th semester course: Fabrication steps for NMOS, CMOS AND BIPOLAR JUNCTION TRANSISTOR

1. ICPROCESSING
Neha Sharma
Assistant Professor
Department of Electronics and Communication Engineering
Engineering College Jhalawar (Rajasthan)

2. IC FABRICATION PROCESS FLOW
SILICON
PROCESSING
MASKING
PHOTO-
LITHOGRAPHY
ETCHING
DIFFUSION/
IMPLANTATION
DEPOSITION METALLISATION
PLANARISATION
NEHA SHARMA | ECE

3. Integrated circuits
Anintegrated circuitormonolithic integrated circuit(also
referred to as anIC, achip, or amicrochip) is a set
ofelectronic circuitson one small flat piece (or "chip")
ofsemiconductormaterial that is normallysilicon. The
integration oflarge numbersof tinyMOS transistorsinto a
small chip results in circuits that are orders of magnitude
smaller, faster, and less expensive than those constructed of
discreteelectronic components.
NEHA SHARMA | ECE

4. NMOSFABRICATION
S. M. Kang and Y. Leblebici. (2003). CMOS Digital Integrated Circuits,
New Delhi: TMH
NEHA SHARMA | ECE

5. a)Silicon substrate
b)Oxidation
c)Etching of oxide layer
d)Gate oxide deposition
Ref: Kang SM, LeblebiciY. CMOS digital integrated circuits. Tata
McGraw-Hill Education; 2003.
NEHA SHARMA | ECE

6. (e) Polysilicon deposition for GATE formation
(f) Patterning
(g) Etching for imterconnections
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7. (h) Ion implantation for source and drain
Region.
(i) Insulating oxide deposition
(j) Etching contact windows for source and
drain
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8. (k) Metallisation
(l) Etching out metal contacts.
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9. CMOS FABRICATION
Rabaey, J. M.; Chandrakasan, A.; Nikolic, B. (2003). Digital integrated
circuits: a design perspective, 1996, Prentice-Hall International Inc.
NEHA SHARMA | ECE

10. Simplifiedprocess
sequenceforthe
manufacturingofan
dual-well CMOS
circuit.
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11. NEHA SHARMA | ECE

12. NEHA SHARMA | ECE

13. NEHA SHARMA | ECE

14. NEHA SHARMA | ECE

15. BJTFABRICATION
Using junction isolation technique
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16. BIPOLAR IC FABRICATION STEPS
Ref: http://www.circuitstoday.com/bipolar-ic-manufacturing-process
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17. 1. Implantation of the Buried Layer
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18. 2. Epitaxial silicon layer
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19. 3. P+ isolation diffusion (Junction
Isolation)
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20. 4. Base Diffusion
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21. 5. Emitter Diffusion
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22. 6. P+ ohmiccontact7. Metal deposition
and etching
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23. 8. Passivation layer
Covering the entire wafer with glass and opening the area over bond pads
(which requires another mask).
Ref: http://pallen.ece.gatech.edu/Academic/ECE_4430/Summer_2004/L160A-BJTTech(2-UP).pdf
NEHA SHARMA | ECE