instruction set explanation of 8085 microprocessor

The **8085 microprocessor** is a fundamental component of early computing systems and embedded applications, known for its simplicity and efficiency. This presentation provides a **detailed study of the 8085 instruction set**, focusing on its classification, execution process, and impact on processor flags. The **8085 instructions** are categorized based on their **length and functionality**, helping users understand how different operations are executed at the machine level. The instruction set is broadly classified into **one-byte, two-byte, and three-byte instructions**. One-byte instructions contain only the opcode, while two-byte instructions include an additional operand, and three-byte instructions use two extra bytes to specify memory addresses.

The **data transfer instructions** enable the movement of data between registers, memory, and I/O devices without affecting the processor flags. Examples include **MOV, MVI, LDA, STA, and LXI**. In contrast, the **arithmetic instructions** perform mathematical operations like addition, subtraction, increment, and decrement, directly modifying flags such as Zero (Z), Carry (CY), Sign (S), and Parity (P). Instructions like **ADD, ADC, SUB, SBB, and DAD** fall under this category. Additionally, the **logical instructions** such as **ANA, ORA, XRA, and CMA** execute bitwise operations, affecting specific flags while preserving others.

This presentation also explores the **branching and control instructions**, which are essential for decision-making and program flow control in assembly language programming. Unconditional branching instructions like **JMP and CALL** allow direct jumps, while conditional branching instructions like **JZ, JNZ, JC, and JNC** execute based on flag conditions. **Stack and machine control instructions** such as **PUSH, POP, HLT, and NOP** play a vital role in processor operation and subroutine execution.

By analyzing these instructions, this presentation provides a **clear understanding of how the 8085 microprocessor executes commands at the hardware level**. Whether you are a student, researcher, or professional in microprocessor-based system design, this guide will enhance your knowledge of **8085 assembly programming and system architecture**.

1. 8085 Instruction Set Data Transfer, Arithmetic And Logical Instruction Subject:COA (4350701) Prepaid By: Guided By: Goswami Harshit(229920307020) Prof.Kalpit Chandpa Hadiya Kaushik(229920307023) Het Trivedi(229920307059) Computer Department GMB Polytechnic Rajula 1

2. Classification of Instructions Based on the parameters Data Transfer Instruction Arithmetic Instructions Logical Instructions Instruction Length 1 Byte instructions 2 Byte instructions 3 Byte instructions

3. Logical Instructions (NOT, AND, OR, EXOR)

4. The classification of 8085 Instructions based on length One Byte Instructions: in one byte only opcode no operand Example Opcode Operand CMA HLT NOP

5. 8085 Instruction Types Two Byte Instructions: First byte specifies opcode and second byte specifies operand Example Opcode Operand MVI A, 07

6. 8085 Instruction Types Three Byte Instructions: First byte specifies opcode and the following two bytes specifies address Example Note: Second byte is lower order address Third byte is higher order address Opcode Operand LDA 2085H

7. Data Transfer Instructions

8. Example Instruction: MOV A, B Register contents before Execution 9A h 89 h A B Register contents after Execution 89 h 89 h A B Note: No flags are modified during the execution of data transfer instruction.

9. Example Instruction: MOV C, M Register contents before Execution 9A h 8500 h C HL 84FF 7A h 8500 C2 h 8501 8502 45 h F4 h MEMORY Register contents after Execution C2 h C 8500 h HL 84FF 7A h 8500 C2 h 8501 8502 45 h F4 h MEMORY

10. Example Instruction: MVI B, 18 h Register contents before Execution 9A h B Register contents after Execution 18 h B

11. Example Instruction: LDA 2005 h Register contents before Execution 87 h A 2003 7A h 2004 C2 h 2005 2006 45 h F4 h MEMORY Register contents after Execution 45 h A 2003 7A h 2004 C2 h 2005 2006 45 h F4 h MEMORY

12. Example Instruction: STA 2005 h Register contents before Execution 87 h A 2003 7A h 2004 C2 h 2005 2006 45 h F4 h MEMORY Register contents after Execution 87 h A 2003 7A h 2004 C2 h 2005 2006 87 h F4 h MEMORY

13. Example Instruction: LDAX D 401F 7A h 4020 C2 h 4021 4022 45 h F4 h MEMORY Register contents before Execution 2B h A 4020 h DE Register contents after Execution C2 h A 401F 7A h 4020 C2 h 4021 4022 45 h F4 h MEMORY 4020 h DE

14. Example Instruction: STAX B 401F 7A h 4020 C2 h 4021 4022 45 h F4 h MEMORY Register contents before Execution A4 h A 4020 h BC Register contents after Execution A4 h A 401F 7A h 4020 A4 h 4021 4022 45 h F4 h MEMORY 4020 h BC

15. Example Instruction: LHLD 2005 h 2004 7A h 2005 C2 h 2006 2007 45 h F4 h MEMORY Register contents before Execution 74F1 h HL Register contents after Execution 2004 7A h 2005 C2 h 2006 2007 45 h F4 h MEMORY 45C2 h HL

16. Example Instruction: SHLD 2005 h 2004 7A h 2005 A4 h 2006 2007 45 h F4 h MEMORY Register contents before Execution 74F1 h HL Register contents after Execution 2004 7A h 2005 F1 h 2006 2007 74 h F4 h MEMORY 74F1 h HL

17. Example Instruction: LXI B, 1122 h Register contents before Execution 76DA h BC Register contents after Execution 1122 h BC

18. Example Instruction: XCHG Register contents before Execution 1234 h 5678 h HL DE Register contents after Execution 5678 h 1234 h HL DE

19. Arithmetic Instructions

20. Example Instruction: ADD B Register contents before Execution 9A h 89 h A B Register contents after Execution 23 h 89 h A B Note: All flags are affected during the execution of arithmetic instruction. 1 0 0 1 1 0 1 0 1 0 0 0 1 0 0 1 0 0 1 0 0 0 1 1 Flag: S=0, Z=0, AC=1 , P=0 and CY=1

21. Example Instruction: ADC B Register contents after Execution 24 h 89 h A B 0 0 1 0 0 1 0 0 Register contents before Execution 9A h 89 h A B Flag: S=0, Z=0, AC=0 , P=0 and C=1 1 0 0 1 1 0 1 0 1 0 0 0 1 0 0 1 1 Flag: S=0, Z=0, AC=1 , P=1 and CY=1 0 0 1 0 0 0 1 1

22. Example Instruction: ADI B2 h Register contents after Execution 76 h A 0 1 1 1 0 1 1 0 Register contents before Execution C4 h A Flag: S=0, Z=0, AC=0, P=0 and CY=0 1 1 0 0 0 1 0 0 1 0 1 1 0 0 1 0 Flag: S=0, Z=0, AC=0 , P=0 and CY=1

23. Example Instruction: ACI 15 h Register contents after Execution 4E h A 0 1 0 0 1 1 1 0 Register contents before Execution 38 h A Flag: S=0, Z=0, AC=0 , P=0 and C=1 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 1 Flag: S=0, Z=0, AC=0 , P=1 and CY=0 0 1 0 0 1 1 0 1

24. Example Instruction: DAD B Register contents before Execution 2233 h HL 1122 h BC Register contents after Execution 3355 h HL 1122 h BC Note: No flags are affected except Carry Flag.

25. Example Instruction: SUB M Register contents before Execution 20 h 8500 h A HL 84FF 7A h 8500 08 h 8501 8502 45 h F4 h MEMORY Register contents after Execution 18 h A 8500 h HL 84FF 7A h 8500 08 h 8501 8502 45 h F4 h MEMORY Flag: S=0, Z=0, AC=0 , P=0 and CY=1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 0 Flag: S=0, Z=0, AC=1 , P=1 and CY=0

26. Example Instruction: SBB B Register contents after Execution 1F h 20 h A B 0 0 0 1 1 1 1 1 Register contents before instruction 40 h 20 h A B Flag: S=0, Z=0, AC=0 , P=0 and C=1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 Flag: S=0, Z=0, AC=1, P=0 and CY=0

27. Example Instruction: SUI 13 h Register contents after Execution F2 h A 1 1 1 1 0 0 1 0 Register contents before Execution 05 h A Flag: S=0, Z=0, AC=0 , P=0 and CY=0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 1 1 Flag: S=1, Z=0, AC=0, P=0 and CY=1

28. Example Instruction: SBI 13 h Register contents after Execution 04 h A 0 0 0 0 0 1 0 0 Register contents before Execution 18 h A Flag: S=0, Z=0, AC=0 , P=0 and C=1 0 0 0 1 1 0 0 0 0 0 0 1 0 0 1 1 1 Flag: S=0, Z=0, AC=0, P=0 and CY=0

29. Example Instruction: INR E Register contents before Execution 1C h E Register contents after Execution 1D h E Note: Except Carry Flag, all flags are affected depend upon the result.

30. Example Instruction: DCR M Register contents before Execution 8500 h HL 84FF 7A h 8500 08 h 8501 8502 45 h F4 h MEMORY Register contents after Execution 8500 h HL 84FF 7A h 8500 07 h 8501 8502 45 h F4 h MEMORY Note: Except Carry Flag, all flags are affected depend upon the result.

31. Example Instruction: INX D Register contents before Execution A103 h DE Register contents after Execution A104 h DE Note: No Flags are affected.

32. Example Instruction: DCX H Register contents before Execution FFFF h HL Register contents after Execution FFFE h HL Note: No Flags are affected.

33. Example Instruction: DAA Register contents before Execution 6C h A Register contents after Execution 72 h A Flag: S=0, Z=0, AC=0 , P=0 and CY=0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 1 0 Flag: S=0, Z=0, AC=1 , P=1 and CY=0

34. Logical Instructions

35. Logical Instructions

36. Example Instruction: ANA C Note: S, Z, P flags are affected during the execution of AND instruction. CY=0 AC = 1 0 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 0 0 0 0 1 0 Register contents before Execution 62 h 4A h A C Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Register contents after Execution 42 h 4A h A C Flag: S=0, Z=0, AC=1 , P=1 and CY=0

37. Example Instruction: ANI 15 h 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 Register contents before Execution 62 h A Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Register contents after Execution 00 h A Flag: S=0, Z=1, AC=1 , P=1 and CY=0

38. Example Instruction: ORA C 0 1 1 0 0 0 1 0 0 1 0 0 1 0 1 0 0 1 1 0 1 0 1 0 Register contents before Execution 62 h 4A h A C Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Register contents after Execution 6A h 4A h A C Flag: S=0, Z=0, AC=0 , P=1 and CY=0 Note: S, Z, P flags are affected during the execution of OR instruction. CY=0 AC = 0

39. Example Instruction: ORI 15 h 0 1 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 1 1 Register contents before Execution 62 h A Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Register contents after Execution 77 h A Flag: S=0, Z=0, AC=0 , P=1 and CY=0

40. Example Instruction: XRA E 1 1 1 0 1 1 1 0 0 1 0 1 1 0 1 0 1 0 1 1 0 1 0 0 Note: S, Z, P flags are affected during the execution of XOR instruction. CY=0 AC = 0 Register contents before Execution EE h 5A h A E Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Register contents after Execution B4 h 5A h A E Flag: S=0, Z=0, AC=0 , P=1 and CY=0

41. Example Instruction: XRI 18 h Register contents before Execution C3 h A Register contents after Execution DB h A 1 1 0 0 0 0 1 1 0 0 0 1 1 0 0 0 1 1 0 1 1 0 1 1 Flag: S=0, Z=0, AC=0 , P=0 and CY=0 Flag: S=0, Z=0, AC=0 , P=1 and CY=0

42. Example Instruction: CMA Register contents before Execution 9A h A Register contents after Execution 65 h A 1 0 0 1 1 0 1 0 0 1 1 0 0 1 0 1 Note: No Flags are affected.

43. Example Instruction: RLC Register contents before Execution Register contents after Execution 1 1 1 1 1 1 A CY CY A 1 1 1 1 1

44. Example Instruction: RRC Register contents before Execution Register contents after Execution 1 1 1 1 1 1 A CY CY A 1 1 1 1 1 1 1 1 1 1

45. Example Instruction: RAL Register contents before Execution Register contents after Execution 1 1 1 1 A CY CY A 1 1 1 1

46. Example Instruction: RAR Register contents before Execution Register contents after Execution 1 1 1 1 A CY CY A 1 1 1 1