Instruction set of 8086

1. Agenda: Wednesday, July 2, 2014 Instruction Set of 8086 Instruction Set of 8086 Functional Block Diagram of 80386Dx Pin Description 1

2. Wednesday, July 2, 2014 Instruction Set of 8086 2 Instructions Type of 8086 Data Copy/ Transfer Instruction Arithmetic & Logical Instructions. Branch Instruction. Shift & Rotate Instruction String Manipulation Instructions Machine Control Instructions Flag Manipulation & Processor Control Instructions

3. Wednesday, July 2, 2014 Instruction Set of 8086 3 1. Data Copy/ Transfer Instructions MOV: Transfer data from 1 register/ memory location to other register/memory location. Eg . MOV AX,[2000H]. . . . Direct MOV AX,BX . . . . . . .. . . Register II IN(Input the Port): User for reading an input port AL & AX are allowed destinations for 8 & 16 bit input instructions. Ex . IN AL,o3h . . . Reads data from 8 bit port whose address is 03H & store in AL. III OUT(Output to the Port): User for writing to an output port Ex. OUT o3H, AL . . . Sends data available in AL to port whose address is 03H .

4. Wednesday, July 2, 2014 Instruction Set of 8086 4 IV. PUSH (Push to Stack) : Pushes the contents of specified register/memory location on to the stack. Decrements the stack pointer by 2 and copies a word from a specified source to the location in the stack segment to which the stack pointer points. This instruction does not affect any flag. Ex. PUSH AX . . . . . Decrement SP by 2, copy BX to stack. 2. PUSH DS . . . . Decrement SP by 2, copy DS to stack.

5. Wednesday, July 2, 2014 Instruction Set of 8086 5 Physical SS=2000 Address SP 22H 2 FFFD FFFD 55H 2FFFE FFFE xx 2FFFF FFFF PUSH AX AH AL 55 22 Fig 1: Execution of PUSH instruction

6. Wednesday, July 2, 2014 Instruction Set of 8086 6 V. POP – POP Destination The POP instruction copies a word from the stack location pointed to by the stack pointer to a destination specified in the instruction. The destination can be a general-purpose register, a segment register or a memory location. The data in the stack is not changed. After the word is copied to the specified destination, the stack pointer is automatically incremented by 2 to point to the next word on the stack. The POP instruction does not affect any flag. Ex- POP DX . . . . Copy a word from top of stack to DX; increment SP by 2

7. Wednesday, July 2, 2014 Instruction Set of 8086 7 Physical SS=2000 Address SP 22H 2 FFFD FFFD 55H 2FFFE FFFE xx 2FFFF FFFF POP AX AH AL 55 22 Fig 2: Execution of POP instruction

8. Wednesday, July 2, 2014 Instruction Set of 8086 8 VI. XCHG(Exchange) – XCHG Destination, Source Exchanges the content of a register with the content of another register or with the content of memory location(s). It cannot directly exchange the content of two memory locations. The source and destination must both be of the same type (bytes or words). The segment registers cannot be used in this instruction. This instruction does not affect any flag. Ex. XCHG AX, DX . . . . Exchange word in AX with word in DX

9. Wednesday, July 2, 2014 Instruction Set of 8086 9 VII. LEA(Load Effective Address) Loads E.A formed by destination operands in to specific source operands. Instruction is more useful in ALP rather than machine language. Ex. LEA BX,ADR . . . Offset will transformed to BX * LEA Bx,0005H

10. Wednesday, July 2, 2014 Instruction Set of 8086 10 2. Arithmetic & Logical Instructions. ADD : Adds immediate data or contents of a memory location specified in instruction or register(source ) to the content another register. Source & destination operands can not be memory operands. i.e. memory to memory addition is not possible. Ex. 1. ADD AX,0100H . . . . Immediate 2. ADD AX,BX . . . . . Register 2. ADC ADD with Carry: Same as add. Adds carry flag bit to the result from previous calculations. Ex. ADC AX,BX . . . . Register ADC AX,0001h

11. Wednesday, July 2, 2014 Instruction Set of 8086 11 3. SUB – SUB Destination, Source Subtract the number in some source from the number in some destination and put the result in the destination. The source may be an immediate number, a register or memory location. The destination can also be a register or a memory location. Source and the destination cannot both be memory location. The source and the destination must both be of the same type (bytes or words). Ex. SUB CX, BX . . . . . CX – BX; Result in CX 4. INC Increment : Increases the content of register/ memory location by 1. Ex. INC AX . . . Register 5. DEC Decrement : Decreases the content of register/ memory location by 1. Ex. DEC AX . . . Register

12. Wednesday, July 2, 2014 Instruction Set of 8086 12 Table 1: Logical Instruction

13. Wednesday, July 2, 2014 Instruction Set of 8086 13 AND : Ex- AND AX,0008H Let AX is 3F0FH 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 =3F0F H {AX} AND 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 =0008 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 = 0008 H {AX} OR : Ex- OR AX,0098H Let AX is 3F0FH 0 0 1 1 1 1 1 1 0 0 0 0 1 1 1 1 =3F0F H {AX} OR 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 =0098 0 0 1 1 1 1 1 1 1 0 0 1 1 1 1 1 = 3F9F H {AX}

14. Wednesday, July 2, 2014 Instruction Set of 8086 14 3. Branch/ Control Transfer Instructions Transfer the flow of the execution of the program to the new address specified in the instruction directly or indirectly. II. While executing this instructions CS & IP get loaded with new values corresponding to the location where flow of the execution is transferred Unconditional Control transfer (Branch) Instructions CS & IP are unconditionally modified . (increment counter for instructions ) 2. Conditional(flag) Control transfer (Branch) Instructions CS & IP are conditionally modified. If Result satisfies particular condition then & then only control is transferred.

15. Wednesday, July 2, 2014 Instruction Set of 8086 15 4. Shift & Rotate instruction 1.Shift Logical Right SHR : Perform bit-wise right shifts on the operand word or byte that may reside in register or memory location. Insert ZERO in the shifted position. Bit Position Operand Count=1 Count = 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CF 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Inserted

16. Wednesday, July 2, 2014 Instruction Set of 8086 16 2.Shift Logical Left SHL : Perform bit-wise left shifts on the operand word or byte that may reside in register or memory location. Insert ZERO in the shifted position. Bit Position Operand Count=1 Count = 2 CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Inserted

17. Wednesday, July 2, 2014 Instruction Set of 8086 17 3 . Rotate Right without carry ROR : Perform bit-wise right shifts on the operand either by one or count specified LSB is shifted to CF & simultaneously shifted to MSB. Bit Position Operand Count=1 Count = 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 CF 1 1 1 1 1 1 1 1 1 1 1 x 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

18. Wednesday, July 2, 2014 Instruction Set of 8086 18 4. Rotate Left without carry ROL : Perform bit-wise left shifts on the operand word or byte that may reside in register or memory location. Insert ZERO in the shifted position. Bit Position Operand Count=1 Count = 2 CF 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

19. Wednesday, July 2, 2014 Instruction Set of 8086 19 5.String Manipulation Instructions REP Repeat Instruction Prefix : 1 Instruction is used as a prefix to the other instruction. Use of this instruction will repeat the execution until CX register will become ZERO . Ex- REPE/REPZ(Repeat operation while equal/zero ) 2. CMPS Compare String Byte or String Word : 1. Compare 2 string of bytes or words. Length of the string must be stored in register CX. If both bytes or word are equal then ZERO flag is set .

20. Wednesday, July 2, 2014 Instruction Set of 8086 20 6. Flag Manipulation & Processing(Machine ) Control Instructions Controls the functioning of available hardware inside the processor chip. F.M. Instructions directly modify some of the flags of 8086. Table 2 . flag Manipulation Instruction CLC Clear Carry Flag CMC Complement Carry Flag STF Set Carry Flag CLD Clear directional flag STD Set Directional Flag CLI Clear Interrupt flag STI Set Interrupt Flag

21. Wednesday, July 2, 2014 Instruction Set of 8086 21 3. PC instructions control the bus usage & execution. WAIT Wait for TEST input pin to go low HLT Halt the processor NOP No Operation Performed ESC Escape to external device like NDP(Numeric co-processor) LOCK Bus Lock instruction Prefix Table 2 . Machine Control Instruction

22. Wednesday, July 2, 2014 Instruction Set of 8086 22