Interrupt Processing in Embedded systems

Interrupt Processing in Embedded systems

1. Interrupt Processing
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury
Dr. Shubhajit Roy Chowdhury,
School of Computing and Electrical Engineering,
Indian Institute of Technology Mandi, India
Email: [email protected]

2. Interrupts
•What is an interrupt?
•What does an interrupt do to the “flow of control”
•Interrupts used to overlap computation & I/O
–
Examples would be console I/O, printer output, and disk
accessesaccesses
•
Normally handled by the OS. Thus under UNIX and
NT, rarely coded by ordinary programmers.
–
In embedded systems and real-time systems, part of the
normal programming work.
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

3. Polling versus Interrupt
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

4. Examples of interrupts
Mouse moved.
Disk drive at sector/track position(old days).
Keyboard key pressed.Keyboard key pressed.
Printer out of paper.
Video card wants memory access.
Modem sending or receiving.
USB scanner has data.
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

5. Types of interrupts
Synchronous/Asynchronous: Synchronous if it occurs at the
same place, every time the program is executed with the
same data and memory allocation. Asynchronous interrupts
are those that occur unexpectedly.
Internal/External : Internal interrupts arise from illegal or Internal/External : Internal interrupts arise from illegal or
erroneous use of an instruction or data , also called as traps.
External interrupts arise from I/O devices, timing device,
circuit generated by power supply.
Software/Hardware : Software interrupts is initiated by
executing an instruction .
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

6. Interrupts (Cont’d)
•Why interrupts over polling? Because polling
–
Ties up the CPU in one activity
–
Uses cycles that could be used more effectively
–
Code can’t be any faster than the tightest polling loop
•
Bottom line: an interrupt is an asynchronous
•
Bottom line: an interrupt is an asynchronous
subroutine call (triggered by a hardware event) that
saves both the return address and the system status
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

7. When an Interrupt Occurs
•Finish the current instruction
•Save minimal state information on stack
•Transfer to the interrupt handler, also known
as the interrupt service routine (ISR)as the interrupt service routine (ISR)
But there is more to it than this…How do we
know which device interrupted?
•And what happens if two (or more) devices
request an interrupt at the same time?
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

8. When a program throws an interrupt a device searching
routine is performed. The program is reentered after the
interrupt is handled.
InterruptRegPC+1
PCinterrupt addr
Save the return
address of the
main program
Interrupt
Service
Determine device;
determine whether
Execute the
instructions in Service
Routine
determine whether
input or output;
I/OA or AI/O
instructions in
the service
routine
Interrupt
return
PCreg Restore the
program
control
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

9. General flow
Main
Program
Process in execution
Process requires I/O service
Returns
Interrupt
Service
Routine
I/O
Interrupt
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

10. Interrupts: Overview
•Complex hardware setup
•Needed for multitasking/multiprogramming OS
Bus
•Devices use IRQs to signal interrupt controller
Device
A
Device
B
Interrupt
Controller
CPU
IRQ
IRQ
interrupt
enable bit
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

11. Different types of interrupt systems
Single interrupt systems.
Multiple interrupt systems.
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

12. Single interrupt system

Finish current instruction.

Save program counter in IRL.

Load program counter with content of IHL.
Single-interrupt system:
interrupt signal
program counter
interrupt return location
IRL
1
interrupt handler location
IHL
CPU
2
3
Single-interrupt system:
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

13. Multiple interrupt system
interrupt signal
program counter
IRL1
IRL2
IRL3
IRL4
IRLn
1
Multiple- interrupt system:
1
2
CPU
IRLn
IHL2
IHL3
IHL4
IHLn
IHL1n
3
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

14. Interrupt handlers
Interrupt handlers are the routines that are called when an
interrupt is detected.
Interrupt handlers are usually short sections of code that are Interrupt handlers are usually short sections of code that are
designed to handle the immediate needs of the device and
return control to the operating system or user program.
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

15. Steps in handling interrupts
Disable further interrupts.
Store current state of program.
Execute appropriate interrupt handling routine.
Restore state of program.Restore state of program.
Enable interrupts.
Resume program execution.
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

16. Flowchart of basic interrupt mechanism
Fetch
Instruction
Decode and
Execute instr.
Increment PC
Int request line
active
Interrupt
service
Routine
No
Yes
Restore PC
Store PC
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

17. Masking interrupts
It is sometimes advantageous to disable interrupts while the
processor is performing some critical operation (like handling
another interrupt).
On some systems there may be one or more high priority
interrupts that cannot be masked.
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

18. Interrupt handling –OS ISSUES
When an interrupt is serviced the processor must be able to execute
without being interrupted. It must have the capability of temporarily
disabling the interrupt atomically.
If an interrupt occurs while an interrupt service is ongoing, it is simply
deferred and considered a pending interrupt. It is serviced after the
current request terminates.current request terminates.
Interrupts and traps are assigned priorities.
A check is made for pending interrupt requests after every instruction.
If there is a pending interrupt request, the priority is checked. If it has a
higher priority than the currently running code, it serviced first, otherwise
it is ignored
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

19. Interrupt priority
When multiple I/O devices are present in an interrupt system, two
difficulties must be resolved:
How to handle interrupt requests from more than one device at a time.
Identification of the selected device.Identification of the selected device.
Assigning priority levels to each device means that highest level
priorities will be serviced before lower levels.
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

20. Types of priority implementations
Software Priority : When the polled data is collected by the
service routine the program will then assign an order of
servicing.
Hardware Priority : This implementation selects the ordering
and generates the vectored information that identifies the and generates the vectored information that identifies the
selected device.
Daisy Chain Priority Control : It distributes the priority
selection so that each device has part of the ordering logic
located with the device controller.
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

21. Priority Inversion
•A high priority task is blocked due to a low
priority task
•How can it happen?
–Mutex for shared resource access–Mutex for shared resource access
–Non-preemptive subsystem access
•Network
•System bus
•Secondary storage
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

22. Priority Inversion
Source of the figure: Chenyang Lu, Washington University Saint Louis
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

23. Unbounded Priority Inversion
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

24. What really happened on Mars?
•Repeated resets in
the Mars
Pathfinder
–The Mars Pathfinder mission was
widely proclaimed as "flawless" in
the early days after its July 4th,
1997 landing on the Martian
surface.... But a few days into the
1997 landing on the Martian
surface.... But a few days into the
mission, not long after Pathfinder
started gathering meteorological
data, the spacecraft began
experiencing total system resets,
each resulting in losses of data.
The press reported these failures
in terms such as "software
glitches" and "the computer was
trying to do too many things at
once"....
–For a full story, visit
http://research.microsoft.com/%7Embj/
Mars_Pathfinder/Mars_Pathfinder.html
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

25. Priority Inheritance
•Inherit the priority of the blocked high priority
task
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

26. Priority Inheritance Protocol (PIP)
–If T
L
blocks a higher proirity task T
H
,
priority(T
L
) ←priority(T
H
)
–When T
L
releases a semaphore:
•Return to its normal priority if it doesn’t block
any task
•Return to its normal priority if it doesn’t block
any task
•Otherwise, set priority(P
L
) ← highest priority of
the tasks blocking on a semaphore held by T
L
–Transitive
•T
1
blocked by T
2
: priority(T
2
) ← priority(T
1
)
•T
2
blocked by T
3
: priority(T
3
) ← priority(T
1
)
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

27. Chained Blocking: Problem of PIP
In the worst case, the highest priority task T
1
can be blocked by N lower
priority tasks in the system when T
1
has to access N semaphores to finish
the execution!
Source of the figure: Damir Isovic, Malardaren University, Sweden
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

28. FPGA based Interrupt Controller
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

29. Detailed block diagram of IRQ generator
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

30. Parallel interrupt handling
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

31. The ATMEGA 16 Interrupt Subsystem
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32. ATMEGA 16 Interrupts
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33. Interrupt in ATMEGA 16
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34. Steps to program an interrupt in C
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

35. Using C macro ISR()
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36. External Interrupt: Relevant pins
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

37. External Interrupts: Enabling
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38. External Interrupts: Specifying events
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

39. Interrupt: Example
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40. C Program for external interrupt example
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41. 8259
•8259 is Programmable Interrupt Controller (PIC)
•It is a tool for managing the interrupt requests.
•8259 is a very flexible peripheral controller chip:
–PIC can deal with up to 64 interrupt inputs
–interrupts can be masked
–various priority schemes can also programmed.–various priority schemes can also programmed.
•originally (in PC XT) it is available as a separate IC
•Later the functionality of (two PICs)is in the
motherboards chipset.
•In some of the modern processors, the functionality of
the PIC is built in.
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

42. Pin description
•8-bit bi-directional data bus, one address line is needed,
PIC has two control registers to be programmed, you can think of
them as two output ports or two memory location.
•The direction of data flow is controlled by RD and WR.
•CS is as usual connected to the output of the address decoder.
•Interrupt requests are output on INT which is connected to the INTR
of the processor. Int. acknowledgment is received by INTA.of the processor. Int. acknowledgment is received by INTA.
•IR0-IR7 allow 8 separate interrupt requests to be inputted to the PIC.
•sp/en=1 for master , sp/en=0 for slave.
•CAS0-3 inputs/outputs are used when more than one PIC to
cascaded.
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

43. Block diagram and pin definitions for the 8259A Programmable
Interrupt Controller (PIC)
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury

44. Interfacing the PIC to the 386 and 486 processors.
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45. Priority Resolver
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46. Thank you
SCEE, IIT MANDIDr. Shubhajit Roy Chowdhury