Introduction to CMOS VLSI design Stick diagram.ppt

Introduction to CMOS VLSI design

1. Introduction to
CMOS VLSI
Design
Circuits & Layout

2. CMOS VLSI DesignCircuits and Layout Slide 2
Outline
CMOS Gate Design
Pass Transistors
CMOS Latches & Flip-Flops
Standard Cell Layouts
Stick Diagrams

3. CMOS VLSI DesignCircuits and Layout Slide 3
CMOS Gate Design
Activity:
–Sketch a 4-input CMOS NAND gate

4. CMOS VLSI DesignCircuits and Layout Slide 4
CMOS Gate Design
Activity:
–Sketch a 4-input CMOS NOR gateA
B
C
D
Y

5. CMOS VLSI DesignCircuits and Layout Slide 5
Complementary CMOS
Complementary CMOS logic gates
–nMOS pull-down network
–pMOS pull-up network
–a.k.a. static CMOSpMOS
pull-up
network
output
inputs
nMOS
pull-down
network
Pull-up OFF Pull-up ON
Pull-down OFFZ (float) 1
Pull-down ON0 X (crowbar)

6. CMOS VLSI DesignCircuits and Layout Slide 6
Series and Parallel
nMOS: 1 = ON
pMOS: 0 = ON
Series: both must be ON
Parallel: either can be ON(a)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
OFF OFF OFF ON
(b)
a
b
a
b
g1
g2
0
0
a
b
0
1
a
b
1
0
a
b
1
1
ON OFF OFF OFF
(c)
a
b
a
b
g1 g2
0 0
OFF ON ON ON
(d) ON ON ON OFF
a
b
0
a
b
1
a
b
11 0 1
a
b
0 0
a
b
0
a
b
1
a
b
11 0 1
a
b
g1 g2

7. CMOS VLSI DesignCircuits and Layout Slide 7
Conduction Complement
Complementary CMOS gates always produce 0 or 1
Ex: NAND gate
–Series nMOS: Y=0 when both inputs are 1
–Thus Y=1 when either input is 0
–Requires parallel pMOS
Rule of Conduction Complements
–Pull-up network is complement of pull-down
–Parallel -> series, series -> parallelA
B
Y

8. CMOS VLSI DesignCircuits and Layout Slide 8
Compound Gates
Compound gatescan do any inverting function
Ex: A
B
C
D
A
B
C
D
A BC D
A B
C D
B
D
Y
A
C
A
C
A
B
C
D
B
D
Y
(a)
(c)
(e)
(b)
(d)
(f) Y = (A.B + C.D)’

9. CMOS VLSI DesignCircuits and Layout Slide 9
Example: O3AI
Y = ((A+B+C).D)’

10. CMOS VLSI DesignCircuits and Layout Slide 10
Example: O3AI
Y = ((A+B+C).D)’A B
Y
C
D
DC
B
A

11. CMOS VLSI DesignCircuits and Layout Slide 11
Signal Strength
Strengthof signal
–How close it approximates ideal voltage source
V
DDand GND rails are strongest 1 and 0
nMOS pass strong 0
–But degraded or weak 1
pMOS pass strong 1
–But degraded or weak 0
Thus nMOS are best for pull-down network

12. CMOS VLSI DesignCircuits and Layout Slide 12
Pass Transistors
Transistors can be used as switchesg
s d
g
s d

13. CMOS VLSI DesignCircuits and Layout Slide 13
Pass Transistors
Transistors can be used as switchesg
s d
g = 0
s d
g = 1
s d
0 strong 0
Input Output
1 degraded 1
g
s d
g = 0
s d
g = 1
s d
0 degraded 0
Input Output
strong 1
g = 1
g = 1
g = 0
g = 0

14. CMOS VLSI DesignCircuits and Layout Slide 14
Transmission Gates
Pass transistors produce degraded outputs
Transmission gatespass both 0 and 1 well

15. CMOS VLSI DesignCircuits and Layout Slide 15
Transmission Gates
Pass transistors produce degraded outputs
Transmission gatespass both 0 and 1 wellg = 0, gb = 1
a b
g = 1, gb = 0
a b
0 strong 0
Input Output
1 strong 1
g
gb
a b
a b
g
gb
a b
g
gb
a b
g
gb
g = 1, gb = 0
g = 1, gb = 0

16. CMOS VLSI DesignCircuits and Layout Slide 16
Tristates
Tristate bufferproduces Z when not enabled
EN A Y
0 0
0 1
1 0
1 1A Y
EN
A Y
EN
EN

17. CMOS VLSI DesignCircuits and Layout Slide 17
Tristates
Tristate bufferproduces Z when not enabled
EN A Y
0 0 Z
0 1 Z
1 0 0
1 1 1A Y
EN
A Y
EN
EN

18. CMOS VLSI DesignCircuits and Layout Slide 18
Nonrestoring Tristate
Transmission gate acts as tristate buffer
–Only two transistors
–But nonrestoring
•Noise on A is passed on to YA Y
EN
EN

19. CMOS VLSI DesignCircuits and Layout Slide 19
Tristate Inverter
Tristate inverter produces restored output
–Violates conduction complement rule
–Because we want a Z outputA
Y
EN
EN

20. CMOS VLSI DesignCircuits and Layout Slide 20
Tristate Inverter
Tristate inverter produces restored output
–Violates conduction complement rule
–Because we want a Z outputA
Y
EN
A
Y
EN = 0
Y = 'Z'
Y
EN = 1
Y = A
A
EN

21. CMOS VLSI DesignCircuits and Layout Slide 21
Multiplexers
2:1 multiplexerchooses between two inputs
S D1 D0 Y
0 X 0
0 X 1
1 0 X
1 1 X0
1
S
D0
D1
Y

22. CMOS VLSI DesignCircuits and Layout Slide 22
Multiplexers
2:1 multiplexer chooses between two inputs
S D1 D0 Y
0 X 0 0
0 X 1 1
1 0 X 0
1 1 X 10
1
S
D0
D1
Y

23. CMOS VLSI DesignCircuits and Layout Slide 23
Gate-Level Mux Design

How many transistors are needed?10
(too many transistors)Y SD SD

24. CMOS VLSI DesignCircuits and Layout Slide 24
Gate-Level Mux Design

How many transistors are needed? 2010
(too many transistors)Y SD SD 4
4
D1
D0
S
Y
4
2
2
2Y
2
D1
D0
S

25. CMOS VLSI DesignCircuits and Layout Slide 25
Transmission Gate Mux
Nonrestoring mux uses two transmission gates

26. CMOS VLSI DesignCircuits and Layout Slide 26
Transmission Gate Mux
Nonrestoring mux uses two transmission gates
–Only 4 transistorsS
S
D0
D1
YS

27. CMOS VLSI DesignCircuits and Layout Slide 27
Inverting Mux
Inverting multiplexer
–Use compound AOI22
–Or pair of tristate inverters
–Essentially the same thing
Noninverting multiplexer adds an inverterS
D0 D1
Y
S
D0
D1
Y
0
1
S
Y
D0
D1
S
S
S
S
S
S

28. CMOS VLSI DesignCircuits and Layout Slide 28
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects

29. CMOS VLSI DesignCircuits and Layout Slide 29
4:1 Multiplexer
4:1 mux chooses one of 4 inputs using two selects
–Two levels of 2:1 muxes
–Or four tristatesS0
D0
D1
0
1
0
1
0
1
Y
S1
D2
D3
D0
D1
D2
D3
Y
S1S0S1S0S1S0S1S0

30. CMOS VLSI DesignCircuits and Layout Slide 30
D Latch
When CLK = 1, latch is transparent
–D flows through to Q like a buffer
When CLK = 0, the latch is opaque
–Q holds its old value independent of D
a.k.a. transparent latchor level-sensitive latchCLK
D Q
Latch D
CLK
Q

31. CMOS VLSI DesignCircuits and Layout Slide 31
D Latch Design
Multiplexer chooses D or old Q1
0
D
CLK
Q
CLK
CLK
CLK
CLK
DQ Q
Q

32. CMOS VLSI DesignCircuits and Layout Slide 32
D Latch OperationCLK = 1
D Q
Q
CLK = 0
D Q
Q
D
CLK
Q

33. CMOS VLSI DesignCircuits and Layout Slide 33
D Flip-flop
When CLK rises, D is copied to Q
At all other times, Q holds its value
a.k.a. positive edge-triggered flip-flop, master-slave
flip-flopFlop
CLK
D Q D
CLK
Q

34. CMOS VLSI DesignCircuits and Layout Slide 34
D Flip-flop Design
Built from master and slave D latchesQM
CLK
CLK
CLK
CLK
Q
CLK
CLK
CLK
CLK
D
Latch Latch
D Q
QM
CLK
CLK

35. CMOS VLSI DesignCircuits and Layout Slide 35
D Flip-flop OperationCLK = 1
D
CLK = 0
Q
D
QM
QM
Q
D
CLK
Q

36. CMOS VLSI DesignCircuits and Layout Slide 36
Race Condition
Back-to-back flops can malfunction from clock skew
–Second flip-flop fires late
–Sees first flip-flop change and captures its result
–Called hold-time failureor race conditionCLK1
D
Q1
Flop Flop
CLK2
Q2
CLK1
CLK2
Q1
Q2

37. CMOS VLSI DesignCircuits and Layout Slide 37
Nonoverlapping Clocks
Nonoverlapping clocks can prevent races
–As long as nonoverlap exceeds clock skew
We will use them in this class for safe design
–Industry manages skew more carefully instead 
1

1
1

1

2

2
2

2

2

1
QM
QD

38. CMOS VLSI DesignCircuits and Layout Slide 38
Gate Layout
Layout can be very time consuming
–Design gates to fit together nicely
–Build a library of standard cells
Standard cell design methodology
–V
DDand GND should abut (standard height)
–Adjacent gates should satisfy design rules
–nMOS at bottom and pMOS at top
–All gates include well and substrate contacts

39. CMOS VLSI DesignCircuits and Layout Slide 39
Example: Inverter

40. CMOS VLSI DesignCircuits and Layout Slide 40
Example: NAND3
Horizontal N-diffusion and p-diffusion strips
Vertical polysilicon gates
Metal1 V
DDrail at top
Metal1 GND rail at bottom
32 lby 40 l

41. CMOS VLSI DesignCircuits and Layout Slide 41
Stick Diagrams
Stick diagramshelp plan layout quickly
–Need not be to scale
–Draw with color pencils or dry-erase markers

42. CMOS VLSI DesignCircuits and Layout Slide 42
Wiring Tracks
A wiring trackis the space required for a wire
–4 lwidth, 4 lspacing from neighbor = 8 lpitch
Transistors also consume one wiring track

43. CMOS VLSI DesignCircuits and Layout Slide 43
Well spacing
Wells must surround transistors by 6 l
–Implies 12 lbetween opposite transistor flavors
–Leaves room for one wire track

44. CMOS VLSI DesignCircuits and Layout Slide 44
Area Estimation
Estimate area by counting wiring tracks
–Multiply by 8 to express in l

45. CMOS VLSI DesignCircuits and Layout Slide 45
Example: O3AI
Sketch a stick diagram for O3AI and estimate area
–Y = ((A+B+C).D)’

46. CMOS VLSI DesignCircuits and Layout Slide 46
Example: O3AI
Sketch a stick diagram for O3AI and estimate area
–Y = ((A+B+C).D)’

47. CMOS VLSI DesignCircuits and Layout Slide 47
Example: O3AI
Sketch a stick diagram for O3AI and estimate area
–Y = ((A+B+C).D)’