Introduction to PLL - phase loop lock diagram

introduce about PLL technology. PLL is a multi frequency diagram that apply for ocsillo frequency.

1. Phase-Locked Loop (PLL) EE174 – SJSU Tan Nguyen 1

2. OBJECTIVES Introduction to Phase-locked loop (PLL) Historical Background Basic PLL System Phase Detector (PD) Voltage Controlled Oscillator (VCO) Loop Filter (LF) PLL Applications 2

3. A Phase-Locked Loop (PLL) is a negative feedback system consists of a phase detector , a low pass filter and a voltage controlled oscillator (VCO) within its loop. Its purpose is to synchronize an output signal with a reference or input signal in frequency as well as in phase. In the synchronized or “locked” state, the phase error between the oscillator’s output signal and the reference signal is zero, or it remains constant. If a phase error builds up, a control mechanism acts on the oscillator to reduce the phase error to a minimum so that the phase of the output signal is actually locked to the phase of the reference signal. This is why it is called a PLL. The majority of PLL applications fall into four main categories: Frequency synthesis (Most widely used so PLL is also referred as frequency synthesizer) . Frequency (FM) and phase (PM) modulation and demodulation. Data and carrier recovery. Tracking filters. C lassification of PLLs: Analog or Linear PLL ( LPLL), Digital PLL (DPLL) is Analog PLL with digital phase detector, All-Digital PLL (ADPLL) is a digital loop in two senses: all digital components and all digital (discrete-time ) signals. Introduction to Phase-locked Loop (PLL) 3

4. How Are PLLs Used? 4

5. 1932: Invention of “coherent communication” using vacuum tube, ( deBellescize ) 1943: Horizontal and vertical sweep synchronization in television (Wendt and Faraday) 1954: Color television (Richman) 1965: PLL on integrated circuit 1970: Classical digital PLL 1972: All-digital PLL PLLs today: in every cell phone, TV, radio, pager, computer, … Clock and Data Recovery Frequency Synthesis Clock Generation Clock-skew minimization Duty-cycle enhancement Brief Phase-Locked Loop (PLL) History people.ee.duke.edu/~ mbrooke /defense/Borte. ppt 5

6. Basic PLL System The basic PLL block diagram consists of three components connected in a feedback loop : A Phase Detector (PD) or Phase Frequency Detector (PFD) produces a signal V 𝝓 proportional to the phase difference between the f in and f osc signal. A Loop Filter (LF) filters output voltage V out that controls the frequency of the VCO. A Voltage-Controlled Oscillator (VCO) V out at the input of the VCO determines the frequency f osc of the periodic signal V osc at the output of the VCO A basic property of the PLL atemps to maintain the frequency lock f osc = f in between V osc and V in even if the frequency f in of the incoming signal varies in time. Assume the PLL is in the locked condition, and the frequency f in of the incoming signal increases slightly. The phase difference between the VCO signal and the incoming signal will begin to increase in time. As a result, the filtered output voltage V out increases  the VCO output frequency f osc increases until it matches f in , thus keeping the PLL in the locked condition. 6

7. Lock Range and Capture Range of PLL: Lock Range of the PLL: The range of frequencies where the locked PLL remains in the locked: f min ≤ f in ≤ f max The lock range is wider than the capture range. If the PLL is initially locked, and if f max < f in < f min  the PLL becomes unlocked ( f in ≠ f osc ). When the PLL is unlocked, the f osc = f o where f o is called the center frequency, or the free-running frequency of the VCO. Capture Range of the PLL: The lock can be established again if the incoming signal frequency f in gets close enough to f o . The range of frequencies such that the initially unlocked PLL becomes locked: f o - f c ≤ f in ≤ f o + f c Sometimes a frequency detector is added to the phase detector to assist in initial acquisition of lock . There are three stages of PLL operations: Free Running Stage: When no input is applied at the phase detector, PLL out put frequency is f osc = f o where f o free running frequency of the VCO. Capture Stage: When an input is applied at the phase detector and due to feedback mechanism PLL tries to track the output with respect to the input. Phase Locked Stage: Due to feedback mechanism, the frequency comparison stops when f osc = f in . Stages of PLL Operations 7

8. Linear (Analog) Phase Detector An analog multiplier mixer can be used as a phase detector which compares the phase at each input and generates an error signal, V φ (t), proportional to the phase difference between the two inputs. Recall that the mixer takes the product of two inputs. V φ (t) = cos( ω osc t + φ osc ) cos( ω in t + φ in ) = (1/2) {cos[( ω osc t – ω in t )+ ( φ osc – φ in )] + cos[( ω osc t + ω in t )+ ( φ osc + φ in )]} When loop is locked ( ω osc = ω in )  we have an output proportional to the cosine of the phase difference and one output at twice the input frequency . V φ (t) = (1/2) {cos( φ osc – φ in ) + cos[(2ω osc t )+ ( φ osc + φ in )]} The doubled frequency component will be removed by the low-pass loop filter. Any phase difference then shows up as the control voltage to the VCO, a DC or slowly varying AC signal after filtering. K D is the gain of the phase detector (V/rad). V φ (t) = K D ( φ osc – φ in ) where K D π /2 = V DD /2  K D = V DD / π The averaged transfer characteristic of such a phase detector is shown below. Note that in many implementations, the characteristic may be shifted up in voltage (single supply/single ended). cos( ω in t + φ in ) cos( ω osc t + φ osc ) V φ (t) = ½{cos(φ 0sc – φ in ) + cos[(2ω osc t)+ ( φ osc +φ in )]} High frequency component to be removed by low-pass filter +V DD /2 –V DD /2 8

9. Digital Phase Detector A simple digital phase detector is an XOR gate with logic low output (V φ = 0V) and the logic high output (V φ = V DD ). An example below shows the PLL is in the locked condition where V in and V osc are two phase-shifted periodic square-wave signals at the same frequency f osc = f in = , and with 50% duty ratios . The output of the phase detector is a periodic square-wave signal V φ (t) at the frequency 2f in , and with the duty ratio D φ that depends on the phase difference (t) = [ osc (t) - in (t)] between V in and V osc  D φ = (for XOR) The dc component V φ of the phase detector output can be found easily as the average of V φ (t) over a period V φ = K D is called PD gain (for XOR) where K D = volt/rad for 0 ≤ ≤ The average output rise to V out = when goes from For > , the average output begins to drop.   9

10. Loop Filter The output V φ (t) of the phase detector is filtered by the low-pass loop filter. The purpose of the low-pass filter is to pass the dc and low-frequency portions of V φ (t) and to attenuate high-frequency ac components at frequencies 2 π f in . The simple RC filter has the transfer function: F(s) = = where ω p = and f p = is the cut-off frequency of the filter. If f p << 2f in  the output of the filter V out is approximately equal to the dc component V 𝝓 of the phase detector output. In practice, the high-frequency components are not completely eliminated and can be observed as high-frequency ac ripple around the dc or slowly-varying V o .   In general, the filter output V out as a function of the phase difference. Note that V out = 0 if V in and V osc are in phase ( 𝝓 = 0), and that it reaches the maximum value V out = V DD when the two signals are exactly out of phase ( 𝝓 = ). For 0 ≤ 𝝓 ≤ , V o increases, and for 𝝓 > , V o decreases. The characteristic of periodic in 𝝓 with period 2 . The range 0 ≤ 𝝓 ≤ is the range where the PLL can operate in the locked condition.   10

11. In PLL applications, the VCO is treated as a linear, time-invariant system. To obtain an arbitrary output frequency (within the VCO tuning range), a finite V out is required. Let’s define φ osc – φ in = φ o . The XOR function produces an output pulse whenever there is a phase misalignment. Suppose that an output frequency ω 1 is needed. From the upper right figure, we see that a control voltage V 1 will be necessary to produce this output frequency. The phase detector can produce this V 1 only by maintaining a phase offset φ at its input. In order to minimize the required phase offset or error, the PLL loop gain, K D K O , should be maximized, since φ =   Voltage Controlled Oscillator (VCO) Thus, a high loop gain K D K O is beneficial for reducing phase errors. Note: From Phase detector: V 1 = K D φ  φ = From VCO: V 1 =  φ = =   11

12. PLL 4046 Design Example The filter output V o controls the VCO, i.e., determines the frequency f osc of the VCO output V osc . From PLL 4046 circuit below, the voltage V o controls the charging and discharging currents through capacitor C1. As a result the frequency f osc of the VCO is determined by the V o . The VCO output V osc is a square wave with 50% duty ratio and frequency f osc . The VCO characteristics are adjustable by three components: R1, R2 and C1. When V o = 0, the VCO operates at the minimum frequency f min given approximately by: f min = When V o = V DD , the VCO operates at the maximum frequency f max given approximately by: f max = f min + For f min ≤ f osc ≤ f max , the VCO output frequency f osc is ideally a linear function of the control voltage V o . The slope K o = of the f osc (V o ) characteristic is called the gain or the frequency sensitivity of the VCO, in Hz/V.   For proper operation of the VCO, components C1, R1 and R2 should satisfy: 100pF ≤ C1 ≤ 100nF and 10k Ω ≤ R1, R2 ≤ 1M Ω 12

13. Given PLL 4046 circuit on previous page. Select C1, R1 and R2 so that the VCO operates from f min = 8 kHz to f max = 12 kHz. Find the frequency sensitivity (gain) K O if the VCO characteristic f osc (V o ) is linear for 0 ≤ V o ≤ V DD where V DD = 15V. Select C f and R f so that the cut off frequency of the low-pass filter f p = 1KHz Assume Vin(t) is square-wave signal at frequency f in . Determine voltage Vo for: f in = 9 kHz f in = 10 kHz f in = 11 kHz Solution: Select C1 = 1 nF  R2 = 1 / (1, 032 nF x 8000) ≈ 121 k Ω  R1 = 1 / (1, 032 nF x 4000) ≈ 242 k Ω 2) K O = (12 – 8)kHz / (15 – 0)V = 267 Hz/V or 1676 rad/V Select C f = 10 nF  R f = 1 / (1kHz x 2 π x 10nF) ≈ 16 k Ω For: f in = 9 kHz  Δ V o = Δ f osc / K O = (12 – 9) / 267 = 11.2 V  V O ≈ 3.8 V f in = 10 kHz  Δ V o = Δ f osc / K O = (12 – 10) / 267 = 7.5 V  V O = 7.5 V f in = 9 kHz  Δ V o = Δ f osc / K O = (12 – 11) / 267 3.7 V  V O ≈ 11.3 V PLL Design Example f min =   f max = f min +   13

14. Problem 1. Determine the change in frequency for a voltage controlled oscillator (VCO) with a transfer function of K O = 2.5KHz/V and a DC input voltage change of Δ V O = 0.8V.  Solution: Δf = ΔV O K O  Δf = (0.8 V)(2.5 kHz/V) = 2 kHz Problem 2. Calculate the voltage at the output of a phase comparator with a transfer function of K D = 0.5V/rad and a phase error of V ϴ = 0.75 rads .  Solution: V D = K D V ϴ = (0.5 V/rad)(0.75 rad) = 0.375 V Problem 3. Determine the hold in range, (i.e. the maximum change in frequency) for a phase lock loop with an open loop gain of K V = 20kHz/rad. Solution: Δ f max = K V π/2 = (20 krad ) π/2 rad = 31.4 kHz Problem 4. Find the phase error necessary to produce a VCO frequency shift of Δ f = 10KHz for an open loop gain of K V = 40KHz/rad. Solution: V ϴ = Δ f / K V = 10 kHz / 40 kHz/rad) = 0.25 rad Problem 5: Given f osc = 1.2 MHz at VCO in = 4.5 V and f osc = 380 kHz at VCO in = 1.6 V. Find K o Solution: K o = 2 π x (1.2 MHz – 380KHz) / (4.5V – 1.6V) rad/V = 1,777 krad /s/v Examples 14

15. Consider a PLL with feedback = 1. Forward path gain (open loop gain): G(s) = = where K V = K D K O , F(s) = = Transfer function (close loop gain): H(s) = = = = = = Standard form: H(s) = = Therefore: Natural frequency: = = Damping factor: ζ = = = =   PLL Overall Transfer function 15

16. A phase-locked loop has a center frequency of ω = 10 5 rad⁄s , K O = 10 3 rad/s per V, and K D = 1 V/rad. There is no other gain in the loop. Determine the overall transfer function H(s) for: The loop filter F(s) = 1 (all pass filter). The loop filter F(s) is shown below. Loop filter F(s) as in part b) , XOR for the phase detector and V DD = 5V. Natural frequency and damping factor ζ for part c) Solution: The loop gain K V = K D K O = (10 3 rad/s-V)(1 V/rad) = 10 3 s -1 . The transfer function for F(s) = 1 : H(s) = b) The transfer function for F(s) = : H(s) = = = c) K D = V DD / π = 1.6 V/rad  K V = K D K O = (10 3 rad/s-V)(1.6 V/rad) =1600 s -1 H(s) = = = d) = = = 2010 Hz and ζ = = = 0.63   ω p = 1/RC = 1/(120k Ω x3.3nF) = 2525rad/s  F(s) = =   PLL Examples 16

17. Synthesize PLL We will now add the divider 1/N to the feedback path. This architecture is called an “integer-N” synthesizer. Forward path gain ( Loop gain is reduced by a factor of N ): G(s) = = (Note: In most applications, N is not constant, so K V = K D K O is not a constant – varies with frequency according to the choice of N). Transfer Function: H(s) = = = = = Standard form: H(s) = = Therefore: Natural frequency: = = Damping factor: ζ = = = =   17

18. Phase Lock Loop Applications EE174 – SJSU Tan Nguyen

19. Common PLL Applications Clock multiplier/Clock Generator Input: Fixed frequency clock Output: Multiple of input clock frequency/Multiple of clock outputs Frequency synthesizer (Fractional-N, Integer-N) Input: Fixed frequency clock Output: Clock signal with arbitrary frequency Clock and data recovery Input: Data signal (from a serial link) Output: Digital data as well as clock signal with phase detector is different than other applications FM demodulation Input: Radio signal Output: Demodulated signal

20. Basic PLL

21. Basic Clock Multiplier

22. The resolution of the output frequency is determined by the reference frequency applied to the phase detector. Step size or frequency resolution - the smallest frequency increment possible. To obtain a stable low frequency source is not easy, because a quartz crystal oscillating in kHz region is quite bulky and not practical. A sensible approach is to take a good stable crystal-based high frequency source and an integer-N synthesizer to divide it down. Example: Given an oscillator EXTAL = 10 MHz, a step size/frequency resolution of 200 KHz is required. Determine counter values of R and N to produce outputs f OUT = 900.2, 900.4, … MHz. Solution: Step size/frequency resolution: f REF = 200 KHz = 10 MHz / R  R = 10 MHz / 200 kHz = 50 F OUT = 900.2 MHz = 200 kHz x N  N = 900.2 MHz / 200 kHz = 4501  N = 4501, 4502, … Integer-N Synthesizer

23. Fractional-N allows the resolution at the PLL output to be reduced to small fractions of the PFD frequency as shown below, where the PFD input frequency is 1 MHz. It is possible to generate output frequencies with resolutions of 100s of Hz, while maintaining a high PFD frequency. As a result the N-value is significantly less than for integer-N. Fractional-N Synthesizer N EFF = A: Cycle for N counter B: Cycle for N+1 counter A + B = 10 Toggling between the two integer division ratios, a fractional division ratio can be achieved by time- averaging the divider output. N EFF = = 900.2  

24. Programmable Phase-Locked Loop Clock Generator The FS7140/FS7145 is a monolithic CMOS clock generator/regenerator IC. Via the I2C−bus interface, the FS7140/45 can be adapted to many clock generation requirements. The length of the reference and feedback dividers, their fine granularity and the flexibility of the post divider make the FS7140/45 the most flexible stand alone PLL clock generator available.

25. Four-modulus prescalers To extend the upper frequency range of a frequency synthesizer but still allows the synthesis of lower frequencies. The solution is the four-modulus prescaler . The four-modulus prescaler is a logical extension of the dual-modulus prescaler . It offers four different scaling factors, and two control signals are required to select one of the four available scaling factors. Integer-N Frequency Synthesizers with Prescalers f osc = 10MHz

26. Integer-N Frequency Synthesizers with Prescalers cont. There are three programmable /N counters in the system: /N1, /N2, and /N3 dividers. The overall division ratio is given by: N EFF = 100N 1 + 10N 2 + N 3 where N 3 represents the units, N 2 the tens, and N 1 the hundreds of the division ratio N tot . N 2 and N 3 range: 0 – 9, and N 1 ≥ N 2 and N 3 because w hen the content of N 1 becomes 0, all /N1, /N2 and /N3 counters are reloaded to their preset values, and the cycle is repeated. Output /N2 and /N3 counters are HIGH when counter value ≠ 0 and go LOW when counter value = 0. Note: For a reference frequency f1 = 10 kHz, the lowest frequency to be synthesized is therefore: 100 x f 1 = 1 MHz. Example: We wish to generate a frequency that is 1023 times the reference frequency. The division ratio N tot is thus 1023; hence N 1 = 10, N 2 = 2, and N 3 = 3 are chosen. Both outputs of the /N2 and /N3 counters are now HIGH, a condition that causes the four-modulus prescaler to divide initially by 111. N EFF = 2(111) + 1(101) + 7(100) = 1023 N2: Add 10 N3: Add 1 Divide by 100 1 101 1 110 1 1 111 The four-modulus prescaler can divide by factors of 100, 101, 110, and 111. The internal logic of the four-modulus prescaler is designed so that the scaling factor is determined by control signals “N2: Add 10” and “N3: Add 1” as shown in next table. N1 N2 N3 Div 10 2 3 111 9 1 2 111 8 1 101 7 100 6 100 5 100 4 100 3 100 2 100 1 100 Reload values for N1, N2, N3 10 2 3 111

27. Frequency Synthesis and Frequency Dividers A frequency synthesis technique and frequency dividers are used to generate multiple frequencies from an accurate reference frequency, usually a crystal oscillator. In this manner, the non integer frequencies can be developed. Example: A system requires CPU clock 1.6 GHz, memory clock = 200MHz and I/O bus clock = 400 MHz. A crystal oscillator of 30 MHz is used for f REF . Determine counters /R, /N, /P and /Q. Solution: Choose R = 3  f PFD = 30 MHz / 3 = 10 MHz , N = 160  f OSC = 160 x 10 MHz (CPU), P = 4  f OSC = 1.6 GHz / 4 = 400 MHz (I/O Clock), Q = 8  f OSC = 1.6 GHz / 8 = 200 MHz (Memory). f OSC 30 MHz 10 MHz /160 /8 /4 /3

28. Clock Data Recovery Different Techniques of Data Communication 1. Serial Data Communication: Data bits are transmitted sequentially one by one 2. Parallel Data Communication: Data bits are driven on multiple wires simultaneously . a)     Skew Travelling path length for every bit is going to be different. Due to this some bits can arrive early or before than others which may corrupt the information. b)     Inter symbol interference (ISI) and Cross talk Due to several parallel links ISI and Cross talk is introduced in the system which gets more severe as length of link is increased. So this limits the length of a connection. c)     Limitation of I/O pin count Parallel data communication requires a lot more I/O pins than what is required by serial data communication.

29. A Clock and Data Recovery (CDR) circuit is an essential block in many high-speed wire-linked data transmission applications such as optical communications systems, backplane data-link routing and chip-to-chip interconnection . Sometimes the data is sent over the high speed serial interfaces without an accompanying clock, the receiver needs to recover the clock in order to sample the data on serial lines . The important role of a Clock and Data Recovery (CDR) is to: Detect the transitions in the received data and generates a periodic recovery clock – Clock recovery. Retime the received data which samples noisy data and then regenerates it with less jitter and skew driven by the recovered clock – Data recovery. Note: A primary difference between CDR and PLL is that the incoming data is not periodic like the incoming reference clock of a PLL Clock Data Recovery

30. 30 Phase Detector : Generates an output signal in relation to the phase difference of both inputs Linear – PLL can analyzed in a similar manner as frequency synthesizers Nonlinear – PLL operates as a bang-bang control system (hard to rigorously analyze in many cases) Charge-Pump : Output pulses of PD are converted to current Loop Filter : Integrates the output of the charge pump and produces the control voltage Voltage Controlled Oscillator : Generates a periodic output whose frequency depends on the control voltage Clock Data Recovery

31. 31 Hogge Phase Detector (Linear PD ): Error output, e(t), consists of two pulses with opposite polarity • Positive polarity pulse has an area that is proportional to the phase error between the data and clock • Negative polarity pulse has a fixed area corresponding to half of the clk period • Overall area is zero when data edge is aligned to falling clock edge Phase Detectors in Clock and Data Recovery Circuits

32. 32 Alexander Phase Detector (Bang-Bang PD ): Data is sampled at 3 equidistant points A, B and C • XOR gates combine nodes A, B and C : X = A xor B and Y = B xor C • Performs an early-late detection Clock is early: Y = Low and X = High Clock is late: Y = High and X = Low Phase Detectors in Clock and Data Recovery Circuits

33. 33 Phase Detectors in Clock and Data Recovery Circuits Alexander Phase Detector (Bang-Bang PD):

34. Clock Jitter : Jitter is a shift in the edges of a periodic signal. This breaks the periodicity of the signal. – AC - jitter: The uncertainty of the output phase – DC - phase offset: Undesired difference of the average output phase relative to the input phase. A data bit should be sampled at the centre . It is the optimum position where maximum shift in the edges on either side (from left to right or right to left) can be encountered. However if the shift in an edge becomes greater than half of the bit period then there will be a bit error. Clock w/o jitter Clock w/ jitter Clock Data Recovery Data Jitter: Jitter tolerance is defined as the amount of jitter that the CDR circuit must tolerate on the input data without increasing the bit error rate (BER). If the jitter on the input data varies slowly, the recovered clock will track the transition in the data and always sample the data in the middle of the bit period as shown below. This will guarantee a low BER. If the jitter on the input data varies fast , the recovered clock will not be able to track the transition in the data and will fail to sample the data in the middle of the bit period as shown in Figure 2.14. This will result in a greater BER.

35. Clock Data Recovery

36. Differentiation CDR The steps taken by the algorithm to obtain the recovered data. The first plot is the input data, the second is the differentiated input data. We can see that the peaks occur at the zero crossings of the input data. The third plot is the fullwave rectified differentiated data. This data is used to create a clock, which is then used to create the fourth plot, the regenerated data

37. References: http://www.onsemi.com/pub/Collateral/FS7140-D.PDF http://www.scribd.com/doc/237983665/PLL http://www.delroy.com/PLL_dir/tutorial/PLL_tutorial_slides.pdf Phase Locked Loops 6/e, 6th Edition by Roland Best https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=an535 http://eprints.lancs.ac.uk/52334/1/PLLbook_chapter_final_2.pdf http://www.ti.com/lit/ds/symlink/lm565.pdf PLL-74HC4046_Application_Note%20(1).pdf http://users.ece.gatech.edu/pallen/Academic/ECE_6440/Summer_2003/L170-FreqSyn-I(2UP).pdf http://iris.lib.neu.edu/cgi/viewcontent.cgi?article=1007&context=elec_comp_theses

38. References: ecee.colorado.edu/~ecen4002/manuals/dsp56300family/ch6-pll-clk.pdf http://www.arrowdevices.com/blog/beginners-guide-to-clock-data-recovery/ http://www.twyman.org.uk/clock_recovery/#pn-seq http://web.stanford.edu/class/archive/ee/ee371/ee371.1066/lectures/Old/Older/lect_17_CDR_2up.pdf http://www.seas.ucla.edu/brweb/teaching/215C_W2013/PLLs.pdf http://www.ece.ucsb.edu/~long/ece594a/PLL_intro_594a_s05.pdf http://www.ti.com/lit/an/snoa351/snoa351.pdf http://memo.cgu.edu.tw/jtkuo/files/eelab%202014%28III%29/1230_Lab12_Expxx_PhaseLockedLoop.pdf http://siihr64.iihr.uiowa.edu/MyWeb/Teaching/ece_55141_2013/Homework/HomeworkAssignment08Solution.pdf http://www.freeclassnotesonline.com/VCO-and-PLL-Calculations-HW.php http://ecee.colorado.edu/~ecen4618/lab4.pdf http://www.analog.com/media/en/training-seminars/tutorials/MT-086.pdf www.ti.com/lit/an/swra029/swra029.pdf

39. References: http://www.scribd.com/doc/237983665/PLL http://www.delroy.com/PLL_dir/tutorial/PLL_tutorial_slides.pdf Phase Locked Loops 6/e, 6th Edition by Roland Best https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=an535 http://eprints.lancs.ac.uk/52334/1/PLLbook_chapter_final_2.pdf http://www.ti.com/lit/ds/symlink/lm565.pdf PLL-74HC4046_Application_Note%20(1).pdf http://users.ece.gatech.edu/pallen/Academic/ECE_6440/Summer_2003/L170-FreqSyn-I(2UP).pdf http://iris.lib.neu.edu/cgi/viewcontent.cgi?article=1007&context=elec_comp_theses 39

40. References: http:// scholarworks.sjsu.edu/cgi/viewcontent.cgi?article=8032&context=etd_theses http ://www.scribd.com/doc/237983665/PLL http ://www.seas.ucla.edu/brweb/teaching/215C_W2013/PLLs.pdf http ://www.ece.ucsb.edu/~long/ece594a/PLL_intro_594a_s05.pdf http ://www.ti.com/lit/an/snoa351/snoa351.pdf http ://memo.cgu.edu.tw/jtkuo/files/eelab%202014%28III%29/1230_Lab12_Expxx_PhaseLockedLoop.pdf http ://siihr64.iihr.uiowa.edu/MyWeb/Teaching/ece_55141_2013/Homework/HomeworkAssignment08Solution.pdf http ://www.freeclassnotesonline.com/VCO-and-PLL-Calculations-HW.php http ://ecee.colorado.edu/~ecen4618/lab4.pdf http ://www.eas.uccs.edu /~ mwickert/ece5675/lecture_notes/N5675_1.pdf http:// hft.uni-duisburg-essen.de/arbeiten/Vortrag_Forcan_Milan.pdf https:// ocw.mit.edu/courses/electrical-engineering-and-computer-science/6-976-high-speed-communication-circuits-and-systems-spring-2003/lecture-notes/lec21.pdf https:// pdfs.semanticscholar.org/de17/8a088507a387e98a1dc06ccf628e3015fcd3.pdf 40