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1. ARM Architecture

2. ARM Architecture The ARM is a general purpose 32-bit microprocessor , which offers high performance and very low power consumption. The ARM architecture is based on Reduced Instruction Set Computer (RISC) principles , and the instruction set and related decode mechanism are much simpler than those of micro programmed Complex Instruction Set Computers (CISC).

3. Address Incrementer : used to access the next location address register  (MAR) is the CPU register that either stores the memory address from which data will be fetched to the CPU Branch with link  BL  copies the address of the next instruction (after the  BL  ) into the link register.   Debug Request-DBGREQ Debug Acknowledgement –DBGACK Eclk - Enable clock A barrel shifter is  a digital circuit that can shift a data word by a specified number of bits without the use of any sequential logic , only pure combinational logic

4. The ARM processor has two instruction sets : • The standard 32-bit ARM set. • A 16-bit Thumb set . Thumb mode  allows for code to be smaller, and can potentially be faster if the target has slow memory The ARM 7 processor is based on Von Neman model with a single bus for both data and instructions. Though this will decrease the performance of ARM; it is overcome by the pipe line concept. ARM uses the AMBA bus architecture (Advanced Microcontroller Bus Architecture). This AMBA include two system buses: the AMBA High-Speed Bus (AHB) or the Advanced System Bus (ASB) , and the Advanced Peripheral Bus (APB).

5. The ARM processor consists of   Arithmetic Logic Unit (32-bit) Booth multiplier(32-bit) Barrel shifter Control unit Register file of 37 registers each of 32 bits. In addition to this the ARM also consists of a Program status register of 32 bits, Some special registers like the instruction register, memory data read and write register and memory address register, one Priority encoder which is used in the multiple load and store instruction to indicate which register in the register file to be loaded or stored and Multiplexers etc.

6. The status register is a hardware register that contains information about the state of the processor . Individual bits are implicitly or explicitly read and/or written by the machine code instructions executing on the processor . In computing, the instruction register (IR) or current instruction register (CIR) is the part of a CPU's control unit that  holds the instruction currently being executed or decoded . Registers are the memory locations that the CPU can access directly. The registers contain operands or the instructions that the processor is currently accessing .

7. The memory address register (MAR) is the CPU register that either stores the memory address from which data will be fetched to the CPU registers, or the address to which data will be sent and stored via system bus. if there is more than one input at logic level “1 ” at the same time, the actual output code would only correspond to the input with the highest designated priority Load instructions move data from memory to registers.  Store instructions move data from registers to memory.

8. ARM Registers Data Registers- R0-R15 ARM architecture is inbuilt with register for data processing it has both general purpose and special purpose register as follows R0-R12 -General Purpose Registers R13-R15 -Special function registers of which, R13 - Stack Pointer, refers to entry pointer of Stack. R14 - Link Register, Return address is put to this whenever a subroutine is called. R15 - Program Counter. Stack Pointer : A small register that stores the memory address of the last data element added to the stack or, in some cases, the first available address in the stack .

9. Status Registers CPSR (Current program status register) - status of current execution is stored. SPSR (Saved program Status register) - status of program as well as processor.

10. ARM instructions are 32 bits wide.   Thumb instructions are 16 or 32-bits wide .

11. Load Store Architecture: ARM can support for load store architecture, only load and store instructions access the memory , all other instructions use registers as operands Load : To load a value from memory, you copy the data from memory into a register. Store: To store a value to memory, you copy the data from a register to memory . ARM Buses: Register Bank is connected to ALU via two data paths. A bus B bus

12. Pipeline Pipeline is the mechanism used by the RISC processor to execute instructions at an increased speed . This pipeline speeds up execution by fetching the next instruction while other instructions are being decoded and executed. Fetch: The instruction is fetched from memory and placed in the instruction pipeline .   Decode: The instruction is decoded and the datapath control signals prepared for the next cycle. In this stage the instruction 'owns' the decode logic but not the datapath . Execute: Execute the instruction, generated result is written back into a destination register. The instruction 'owns' the datapath .

13. The typical RISC architectural features of ARM A large uniform register file A load/store architecture, where data-processing operations only operate on register contents , not directly on memory contents. Simple addressing modes, with all load/store addresses being determined from register contents Instruction fields only uniform and fixed-length instruction fields, to simplify instruction decode. Control over both the Arithmetic Logic Unit (ALU) and shifter in most data- processing instructions to maximize the use of an ALU and a shifter Auto-increment and auto-decrement addressing modes to optimize program loops. Load and Store Multiple instructions to maximize data throughput. The amount of data moved successfully from one place to another in a given time period

14. MODES OF OPERATION OF ARM PROCESSOR The ARM uses seven processing modes that are used to run the user task. USER mode FIQ mode and IRQ mode SVC mode: UNDEFINED mode THUMB mode

15. USER Mode:  The user mode is a normal mode, which has the least number of registers. It doesn’t have SPSR and has limited access to the CPSR . current program status register that holds four status bits, negative (N), zero (Z), carry (C), and overflow (O).  The SPSR is used to store the current value of the CPSR  FIQ and IRQ:  The FIQ and IRQ are the two interrupt caused modes of the CPU. The FIQ is processing interrupt and IRQ is standard interrupt. The FIQ mode has additional five banked registers to provide more flexibility and high performance when critical interrupts are handled. SVC Mode:  The Supervisor mode is the software interrupt mode of the processor to start up or reset . Undefined Mode:  The Undefined mode traps when illegal instructions are executed . The ARM core consists of 32-bit data bus and faster data flow. THUMB Mode:  In THUMB mode 32-bit data is divided into 16-bits and increases the processing speed. THUMB-2 Mode:  In THUMB-2 mode the instructions can be either 16-bit or 32-bit and it increases the performance of the ARM cortex –M3 microcontroller. The ARM cortex-m3 microcontroller uses only THUMB-2 instructions.