JFET.pptx

jfet,mosfet

1. JFET

2. Current Controlled vs Voltage Controlled Devices

3. Current Controlled vs Voltage Controlled Devices BJT is current controlled device. FET is voltage controlled device. I c = f( I b ) I d = f( v gs )

4. FET - Introduction BJT is Bipolar device, FET is unipolar device. FET conduction depends either on electrons or holes. Types: n-channel JFET P-channel JFET In n-channel JFET conductivity depends on electrons. In p-channel JFET conductivity depends on holes.

5. Application of FET is approximately the same as BJT. FET can be used as amplifiers and switches. Electric field controls the conduction path of output hence it is called as field effect transistor FETs have high input impedance than BJT FETs are more temperature stable FETs are smaller than BJT

6. Construction and Working of JFET

7. Construction and Working of JFET The above figure represents the n-channel JFET. The major part of the material is made up of n-type materials. It is forming channels between two embedded p-type materials, hence it is called n-channel JFET. There are totally 4- Ohmic contact. The Ohmic contact is a low resistance junction (non-rectifying) provides current conduction from metal to semiconductor and vice versa

8. Construction and Working of JFET The first ohmic contact is the drain (D) terminal. The second ohmic contact is the source(S) terminal. The third and fourth ohmic contact are connected together and one common terminal is taken out and that terminal is called as Gate(G). There are 2 p-n junctions and hence 2 depletion regions are formed. Depletion region will not have any free charge carriers. On varying the width of the depletion regions the flow of electrons from source(S) to drain(D) can be controlled.

9. Construction and Working of JFET The voltage across gate to the source controls the flow of current from the drain to the source and hence it is called as voltage-controlled device.

10. Construction and Working of JFET Vgs = 0V, Vds >0

11. Construction and Working of JFET The width of the depletion region will be increased at the top and remains almost the same at the bottom because the n channel is reverse-biased at the top and forward-biased at the bottom. Increasing the reverse bias voltage will increase the width of the depletion region.

12. Symbol of JFET

13. Pinch-off Voltage

14. Characteristics of FET

15. CHARACTERISTICS OF N-CHANNEL JFET :- There are two important characteristics of a JFET. Drain or VI Characteristics Transfer characteristics

16. Drain Characteristics:-  Drain characteristics shows the relation between the drain to source voltage Vds and drain current Id. In order to explain typical drain characteristics let us  consider the curve with Vgs = 0.V. When Vds is applied and it is increasing the drain current ID also increases linearly up to knee point. This shows that FET behaves like an ordinary resistor.This region is called as ohmic region. ID increases with increase in drain to source voltage. Here the drain current is increased slowly as compared to ohmic region.

17. 4) It is because of the fact that there is an increase in VDS .This in turn increases the reverse bias voltage across the gate source junction .As a result of this depletion region grows in size thereby reducing the effective width of the channel. 5) All the drain to source voltage corresponding to point the channel width is reduced to a minimum value  and is known as pinch off. 6) The drain to source voltage at which channel pinch off occurs is called pinch off voltage( Vp ).

18. PINCH OFF Region:- This is the region shown by the curve  as saturation region. It is also called as saturation region or constant current region. Because of the channel is occupied with depletion region , the depletion region is more towards the drain and less towards the source, so the channel is limited, with this only limited number of carriers are only allowed to cross this channel from source drain causing a current that is constant in this region. To use FET as an amplifier it is operated in this saturation region. In this drain current remains constant at its maximum value IDSS. The drain current in the pinch off region depends upon the gate to source voltage and is given by the relation                                  I d = I dss [1-Vgs/ Vp ] 2 This is known as shokley’s relation.

19. BREAKDOWN REGION:- The region is shown by the curve .In this region, the drain current increases rapidly as the drain to source voltage is increased. It is because of the gate to source junction due to avalanche effect. The avalanche break down occurs at progressively lower value of VDS because the reverse bias gate voltage adds to the drain voltage thereby increasing effective voltage across the gate junction         This causes The maximum saturation drain current is smaller The ohmic region portion decreased. It is important to note that the maximum voltage VDS which can be applied to FET is the lowest voltage which causes available break down.

20. Transfer Characteristics Output Current Vs Input Voltage, keeping Output voltage constant. I D vs V GS , Keeping V DS constant.

21. Transfer Characteristics There are 2 ways of obtaining the transfer characteristics. Using the equation Using the output or drain characteristics.

22. VGS = -5V

23. Pinch off voltage (JFET) in junction field-effect transistors (JFETs), "pinch-off" refers to the threshold voltage below which the transistor turns off. the pinch-off voltage is the value of V ds when the drain current reaches a constant saturation value.

24. The threshold voltage The threshold voltage, commonly abbreviated as V th or V GS ( th ), of a field-effect transistor (FET) is the minimum gate-to-source voltage (V GS ) that is needed to create a conducting path between the source and drain terminals. It is an important scaling factor to maintain power efficiency.

25. MOSFET MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor. It is a type of Field Effect Transistor and it is voltage controlled device. It is also called an Insulated Gate Field Effect Transistor (IGFET). It is used for switching or amplifying electronic signals in electronic devices. It is the most commonly used transistor and it can be used in both analog and digital circuits.

26. Symbol of MOSFET:

27. Symbol of MOSFET: In the Enhancement MOSFET the source and the drain are not connected physically, so in the symbol lines are broken I n the Depletion mode line is continuous. In the N-type the arrow points inside and in the P type arrow points outside.

28. Construction of Enhancement MOSFET:

29. Construction of N channel Enhancement MOSFET: The metallic gate terminal in the MOSFET is insulated from the semiconductor layer by a SiO2 layer or dielectric layer. The MOSFET consists of three terminals, they are source(S), Gate (G), Drain (D) and the body which is called as substrate. The substrate is connected to the source internally.

30. Construction of N channel Enhancement MOSFET: In N channel Enhancement MOSFET the source and drain are of N type semiconductor which is heavily doped and the Substrate is of P type semiconductor.  Majority charge carriers are electrons . The source and drain terminals are physically separated in Enhancement mode.

31. In P channel Enhancement MOSFET the source and drain are of P type semiconductor which is heavily doped the Substrate is of N type semiconductor. Majority charge carriers are holes. 

32. Construction of Depletion MOSFET:

33. Construction of N Channel Depletion MOSFET: In the N Channel depletion MOSFET a small strip of semiconductor of N type connects the source and drain. The source and drain are of N type semiconductor and the Substrate is of P type semiconductor. Majority charge carriers are electrons. The source and drain are heavily doped.

34. Construction of P Channel Depletion MOSFET: In the P Channel depletion MOSFET a small strip of semiconductor of P type connects the source and drain.  The source and drain are of P type semiconductor and the Substrate is of N type semiconductor. Majority charge carriers are holes.

35. Working of N channel Enhancement MOSFET In the enhancement mode the applied Gate voltage is always positive. It crosses the threshold voltage it turns ON. The current is generated due to the movement of majority carriers. In the N channel majority of carriers are electrons and in the P channel majority of carriers are holes. The source is connected to the negative terminal. When the electrons move from source to drain the positive charges form below the dielectric because the repulsive force from the gate combines with each other. When the applied gate voltage is increased the number of majority carriers becomes more than the minority carriers below the dielectric medium. So the majority of carriers overcome the recombination of holes and electrons and the majority of carriers move from source to drain in the channel, which forms the current. Thus the gate voltage controls the concentration of the majority of carriers which is responsible for the formation of the channel.

36. Working of Depletion MOSFET: The depletion MOSFET is ON by default. The source and drain terminals are physically connected. When the gate terminal is connected to the negative terminal and source to the positive terminal, the electrons gets repelled below the dielectric layer. The positive charged carrier from the source gets combined with the majority carrier the electrons in the N type and thus depletion layer is formed the channel resistance increases and the current flow decreases. Thus the increase in gate voltage decreases the drain current. They are inversely proportional. When the negative voltage is further increased it reaches the pinch off mode. When the gate is connected to the positive terminal and the source terminal it operates in the enhancement mode.

37. V-I Characteristics of MOSFET:

38. Cut off region:  No current flows through it and the MOSFET is off. Ohmic region:  Drain current increases when the drain source voltage increases. Used as amplifier in this region. Saturation region:  Drain current is constant for drain source voltage. Used as switch in this region. This occurs when the drain source voltage reaches pinch off voltage. Depletion mode:  The MOSFET is ON by default. When negative voltage is applied to the gate terminal it operates in the depletion mode and when positive voltage is applied, it operates in the enhancement mode. Enhancement mode:  When positive voltage is applied to the gate terminal, it starts conducting and the current starts to flow.

39. Depletion MOSFET Enhancement MOSFET The type of MOSFET where the channel depletes with the gate voltage is know as depletion or simply D-MOSFET. The type of the MOSFET where the channel is enhanced or induced using the gate voltage is known as E-MOSFET. The channel is fabricated during manufacturing. There is no channel during its manufacturing. It conducts current between its source and drains when there is no Gate voltage V GS . It does not conduct current when there is no Gate voltage V GS . Applying reverse voltage to the gate reduces the channel width. Applying reverse voltage does not affect E-MOSFET since there is no channel. Applying forward voltage to the gate increases the channel width. Applying the forward voltage generates and increases the width of the channel. It can work in both depletion and enhancement mode. It can only work in enhancement mode. It is a normally ON transistor. It is a normally OFF transistor. It switches OFF with reverse biasing of gate. It switches ON with the forward biasing of the gate. There is no threshold voltage for switching ON the MOSFET. There a threshold voltage at which the MOSFET switches ON. Diffusion or subthreshold current does not exist. E-MOSFET has sub-threshold current leakage between its source and drain.

40. Load line analysis of JFET

41. Types of Biasing in FET Fixed Bias Configuration Self-bias Configuration Voltage divider Bias Source bias

42. Fixed Bias Configuration

43. Fixed Bias Configuration N- Channel FET is used in the above diagram for forming Fixed bias configuration. In the N-Channel FET the gate will be of P-type and it is reverse biased. Two biasing voltages VDD and VGG are used. C1 and C2 are the coupling capacitors. V1 is the input voltage and V2 is the output voltage for the amplifier circuit. In case of FET VGS is the input voltage and VDS is the output voltage

44. Fixed Bias Configuration In this biasing we are using DC sources (VDD and VGG) so we will discuss DC analysis. As we are discussing DC analysis, the reactance of the capacitors C1 and C2 will be For DC signal frequency will be not be there and hence the frequency is zero.  X c = ∞

45. Fixed Bias Configuration So the coupling circuit C1 and C2 will act as open circuit.

46. Fixed Bias Configuration

47. Fixed Bias Configuration Since gate is reverse biased, input impedance will be high and hence the gate current is zero.

48. Hence RG can be removed and act like a short circuit.

49. Self-bias Configuration

50. Self-bias Configuration In Self-bias, we will be having a single voltage biasing circuit(VDD). Source Resistance is present in self biasing circuit, where us it is not there in the fixed biasing circuit.

51. Voltage divider Bias

52. Voltage divider Bias C1, C2 – Coupling capacitor.( blocks DC signal allows AC signal) Cs – Bypass capacitor. ( shorts AC signal to ground, allows DC signal)

53. Source Biasing

54. Source Biasing

55. Source Biasing

56. Source Biasing

57. JFET Small Signal Model Small Signal Model is used for the analysis of a given amplifier circuit by drawing its equivalent circuit.

58. There is no current or resistance in the input side as the gate is always reverse biased.