Lecture 04 wafer technology & basics of cmos

ICE 4010: Micro Electro Mechanical Systems: Wafer Technology & Basics of CMOS

1. Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
ICE 4010: MICRO ELECTRO
MECHANICAL SYSTEMS (MEMS)
Lecture #04
Wafer Technology & Basics of CMOS
Dr. S. Meenatchi Sundaram
Email: [email protected]
1

2. Wafer Technology
2 Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
M
Making wafers is a closely guarded secret and it is possibly
even more difficult to see a wafer production than a single Si
crystal production.
M
First, wafers must all be made to exceedingly tight geometric
specifications. Not only must the diameter and the thickness be
precisely what they ought to be, but the flatness is constrai ned
to about 1 m.
M
This means that the polished surface deviates at most about 1
m from an ideallyflat reference plane. M
And this is not just true for one wafer, but for all 10,000 or so
produced daily in one factory. The number of Si wafers sold in
2001 is about 100,000,000 or roughly 300,000 a day! Only
tightly controlled processes with plenty of know-how and
expensive equipment will assure these specifications. The
following picture gives an impression of the first step of a
many-step polishingprocedure.

3. Wafer Technology
3 Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

4. Wafer Technology
4 Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
Diameter
(mm/in)
Thickness
(mm)
100/4 0.5
150/6 0.75
200/8 1
300/12 0.75

5. Wafer Orientation
5 Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
M
Wafers are grown on crystals that have a regular crystal
structures. M
When they are sliced from the crystal, the surface is alignedin
one of several relative directions,known as the
orientation orientation orientation orientation
.
M
This is also referred to as the growth plane of the crystalline
silicon. M
The orientation is important for the electronic properties of the
wafer. Ion implantation depths depend on the orientation and
itwill affect the paths for transport.
M
The different planes have different arrangements of atoms and
lattices so it will affect the way the electricity travels in the
circuit.
M
The orientations of silicon wafers are classified using
Miller
indices
. These indices include such descriptions as (100), (111),
and (110).

6. Wafer Orientation
6 Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
x
y
z
(100)
x
y
z
(110)
x
y
z
(111)

7. Wafer Flats
7 Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
M
Wafers had flats,and the flats tell you two things:
o
Thedopingtypeofthewafer(n-orp-type)
o
Theorientationofthewafer:{100}or{111}
M
While this is trivial information, consider: All wafers, wh atever
doping type or crystal orientation,lookexactly the same!

8. CMOS Transistors
8
• CMOS is also sometimes referred to as complementary-
symmetrymetal–oxide–semiconductor(orCOS-MOS).
• The words "complementary-symmetry" refer to the fact that the
typical design style with CMOS uses complementary and
symmetrical pairs of p-type and n-type metal oxide
semiconductor field effect transistors (MOSFETs) for logic
functions.
• Two important characteristics of CMOS devices are high noise
immunityandlowstaticpowerconsumption.
• Since one transistor of the pair is always off, the series
combination draws significant power only momentarily during
switchingbetweenonandoffstates.
Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

9. CMOS Transistors
9
• Consequently, CMOS devices do not produce as much waste
heat as other forms of logic, for example transistor–transistor
logic(TTL)orNMOSlogic,whichnormallyhavesomestanding
currentevenwhennotchangingstate.
• CMOSalsoallowsahighdensityoflogicfunctionsonachip.
• ItwasprimarilyforthisreasonthatCMOSbecamethemostused
technologytobeimplementedinVLSIchips.
• The phrase "metal–oxide–semiconductor" is a reference to the
physical structure of certain field-effect transistors, having a
metalgateelectrodeplacedontopofanoxideinsulator,whichin
turnisontopofasemiconductormaterial.
• Aluminium was once used but now the material is polysilicon.
Other metal gates have made a comeback with the advent of
high-kdielectricmaterialsintheCMOSprocess.
Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

10. nMOSTransistors
10
• Four terminals: gate, source, drain, body
• Gate –oxide –body stack looks like a capacitor
– Gate and body are conductors
– SiO
2(oxide) is a very good insulator
– Called metal –oxide –semiconductor (MOS) capacitor
Dr. S.Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+

11. nMOSOperation
11
• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
0
S

12. nMOSOperation Contd…
12
• When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inserts a channel under gate to n-type
– Now current can flow through n-type silicon from source
through channel to drain, transistor is ON
Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
n+
p
Gate Source Drain
bulk Si
SiO
2
Polysilicon
n+
D
1
S

13. pMOSOperation
13
• Similar, but doping and voltages reversed
– Body tied to high voltage (V
DD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
SiO
2
n
Gate Source Drain
bulk Si
Polysilicon
p+
p+

14. Power Supply Voltage
14
• GND = 0 V
• In 1980’s, V
DD= 5V
• V
DDhas decreased in modern processes due to scaling
– High V
DDwould damage modern tiny transistors
– Lower V
DDsaves power (Dynamic power is proportional to
C.V
DD
2.
f.a)
• V
DD= 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal

15. Transistors as Switches
15
• We can view MOS transistors as electrically controlled
switches
• Voltageatgatecontrolspathfromsourcetodrain
Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
g
s
d
g = 0
s
d
g = 1
s
d
g
s
d
s
d
s
d
nMOS
pMOS
OFF
ON
ON
OFF

16. CMOS Inverter
16 Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A Y
0
1
V
DD
A Y
GND
A Y

17. CMOS Inverter
17 Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A Y 0 1 1 0
V
DD
A=
0
Y=
1
GND
OFF
ON
A Y

18. CMOS Inverter
18 Dr. S. Meenatchi Sundaram, Department of Instrumentation & Control Engineering, MIT, Manipal
A Y
0 1
1 0
V
DD
A=
1
Y=
0
GND
ON
OFF
A Y