lecture_32.ppt for PD and the vlsi design

Vlsi PD

1. EE434
ASIC & Digital Systems
Jacob Murray
School of EECS
Washington State University
[email protected]

2. Lecture 32
Test Methodologies

3. Conceptual Architecture of Core Test
•Three separate elements
in the embedded core
test infrastructure.
–Test pattern source and
sink
–Test Access Mechanism
–Core test wrapper

4. Implementation of TAM
•When implementing a TAM, we have the following
options
–A TAM can either reuse existing functionality to transport
test patterns or be formed by dedicated test access
hardware.
–A TAM can either go through other modules on the IC or
pass around those other modules.
–One can either have an independent access mechanism per
core, or share an access mechanism with multiple cores.
–A test access mechanism can either be a plain signal
transport medium, or may contain certain intelligent test
control functions.

5. Reuse of Boundary scan test
•A scan chain around embedded cores.
•It provides access for the core-internal tests as well as
intercore interconnect testing.
•Boundary scan test has the advantage that it builds on an
existing method.
•Drawback: Single bit for test control and test data access
path, does not allow trade off between bandwidth and test
time.

6. Test Rail Architecturewrapper
Core A
bypass
wrapper
Core B
bypass
wrapper
Core C
bypass
wrapper
Core D
bypass

7. Test Rail
•Combines the strength of both the test bus and boundary
scan test approaches.
•One or more test rails of varying width per IC –trade off
between test time and silicon area.
•Multiple cores can be daisy chained into one test rail.
•Per core there is a test rail bypass-allows user to test each
core sequentially or multiple cores in parallel –trade off
between diagnostic resolution and test time.

8. Test Rail (cont’d.)
•Capable of transporting test stimuli and responses for
synchronous digital tests
•Test Rail width relates to following:
–Host pins
–Test time
–Silicon area
•Number of host pins available to accommodate test
signals is given

9. Test-Rail ConnectionsCore A
Core B Core C
16
16
16
16
16
16
16 CORE D
CORE E
CORE F
10
2
8
10

10. Wrapper
•Interface between the embedded core and its
system chip environment.
•It connects the core terminals both to the rest of
the IC, as well as to the TAM.
•It is implemented on chip.

11. Test Shell: An Example of Wrapper
•Three levels of hierarchy
•IP module
•Test Shell
•Host
•IP module is the actual reusable core
•Test Shell is the wrapper of the core
•Host is the SOC environment in which the core is
embedded

12. Three levels of hierarchyHOST
Test Shell Test Shell
IP 1 IP 2

13. Host -Test Shell InterfaceSHELL
IP
bypass
FUNCTIONAL
INPUTS
DIRECT
TEST
INPUTS
TEST RAIL
INPUTS
FUNCTIONAL
OUTPUTS
DIRECT
TEST
OUTPUTS
TEST RAIL
OUTPUTS

14. Host -Test Shell Interface (cont’d.)
The interface between host and Test Shell consists of
three types of input/output terminals:
•Functional inputs/outputs: -these are the normal
inputs/outputs of the IP module
•Test Rail inputs/outputs: -handles the test data
transport for all synchronous digital tests
•Direct test inputs/outputs: -only non-synchronous or
non-digital test signals

15. Test Shell -Control Mechanism
•The TCM is meant to control the operation of the Test Shell
•Two types of test control signals exist:
–Pseudo-static test control signals -these signals set up the
conditions for a certain test (e.g. IEEE 1149.1 type signals)
–Dynamic test control signal like scan-enable

16. Wrapper Standardization -P1500
•TAM Source/Sink
•From chip I/O and from test bus, test rail, BIST, etc.
•TAM In/Out
•0 to n lines for parallel and/or serial test data, or test control
•Standard P1500 Serial Access & Control
•From chip-level TAP controller, chip I/O, etc.

17. P1500 Core Test Requirements
Test Functions at Core Terminals

18. Wrapper Standardization -
P1500(cont’d.)

19. P1500 Wrapper Instruction Register
Proposed Required Instructions
•Normal
–Wrapper cells allow normal core inputs/outputs to pass through the
wrapper for normal system operation
•Core Test
–Wrapper cells are configured to disable the core’s normal mode & connected
to TAM and/or wrapper serial input/output for core test
–Sources & sinks, and core test methods are user defined
•Serial External Test
–Wrapper cells are configured to disable the core’s normal mode, and are
connected serially between the wrapper serial input/output
•Isolation
–Wrapper cells are configured to disable the core’s normal mode, and enable
setting of appropriate core inputs or outputs to constrained and/or disabled
values for core isolation

20. P1500 Wrapper Registers
•Standard P1500 protocol for Wrapper Registers will provide for:
•Parallel capture of input data into the selected register
•Serial shift of the register from serial input to serial output
•Update scan-in data of register to a parallel update stage
•Required for Wrapper Instruction Register and optional for others

21. P1500 Wrapper Registers
Standard Serial Scan Path Configuration
•Serial Control lines enable & perform scan, and select between:
•Wrapper Instruction Register (WIR)
•Or other Data Registers (DRs), e.g. Wrapper Cell Register, Bypass, etc.
•Updated WIR then selects between DRs

22. P1500 Wrapper Connection

23. P1500 TAM Connection Example

24. P1500 Wrapper Interface Port(WIP)
•WIP is used to access the WIR,Bypass and other data registers

25. Block level overview of P1500
wrapper

26. P1500 wrapper configurations

27. P1500 wrapper configurations

28. P1500 wrapper configurations

29. P1500 wrapper configurations

30. P1500 wrapper configurations

31. Convergence of P1500 and Test RailBypass
Register
Tam_out[0:n]
Functional inputs
[
0
:
m
]
scan chain 0
scan chain 1
TEST CONTROL
BLOCK
SERIAL IN SERIAL OUT
Functional
outputs[0:p]
CONTROL
SIGNALS
Tam
_
in
[
0
:
n
]

32. Example of application
cf. IEEE P1500 Standard

33. Example of application (serial
intest)
cf. IEEE P1500 Standard

34. Example of application (bypass)
cf. IEEE P1500 Standard

35. Example of application (serial
extest)
cf. IEEE P1500 Standard

36. Example of application (parallel
extest, intest)
cf. IEEE P1500 Standard

37. P1500 Wrapper Cell Example
Dedicated Output Cell with Update Stage & TAM-Out

38. P1500 Wrapper Cell Example
Dedicated Input Cell with Update Stage & TAM-In

39. WBR CELLD Q D Q D Q
FUNCTIONAL INPUT/
OUTPUT (FROM
SYSTEM/CORE)
TAM INPUT
CLOCK
CAPTURE
UPDATE
SHIFT OUT
FUNCTIONAL INPUT
(TO CORE)/OUTPUT
APPLY
SHIFT

40. WIR CELLD Q D Q D Q
WSI OR FROM
PREVIOUS CELL
CLOCK
SYSTEM CAPTURE
SYSTEM UPDATE
WSO OR TO
NEXT CELL
INSTRUCTION
BIT (GOING TO
FSM)

41. FSMBYPASS
NORMAL
SHIFT
READ
CAPTURE
TEST APPLY
update
_
wir
=
1
update_wir = 0
update_wir = 1
update_wir = 0
update_wir = 1
update_wir = 0
curr_ins =
BYPASS
curr_ins = SHIFT
curr_ins =
NORMAL
curr_ins =
TEST APPLY

42. Test control of multiple cores
•Control signals are common to each core
•scheduling of core test
•control signals are applied accordingly
•some kind of control mechanism either through a system
FSM, embedded system controller or even external
control from ATE