LOGIC GATES AND DISCRETE TTL SIMULATIONS.pptx

SIMULATIONS

1. A B OUT A1 SIMULATION BY: CHRISTIAN P. FEDERE C D OUT 1 E F OUT 1 G H OUT 1 1 1

2. A B OUT DIODE LOGIC OR GATE SIMULATION BY: CHRISTIAN P. FEDERE C D OUT 1 1 E F OUT 1 1 G H OUT 1 1 1

3. DIODE TRANSISTOR LOGIC NOT GATE SIMULATION BY: CHRISTIAN P. FEDERE A OUT 1 B OUT 1

4. A B OUT TRANSISTOR LOGIC AND GATE SIMULATION BY: CHRISTIAN P. FEDERE

5. A B OUT 1 TRANSISTOR LOGIC AND GATE SIMULATION BY: CHRISTIAN P. FEDERE

6. A B OUT 1 TRANSISTOR LOGIC AND GATE SIMULATION BY: CHRISTIAN P. FEDERE

7. A B OUT 1 1 1 TRANSISTOR LOGIC AND GATE SIMULATION BY: CHRISTIAN P. FEDERE

8. A B OUT TRANSISTOR LOGIC OR GATE SIMULATION BY: CHRISTIAN P. FEDERE

9. TRANSISTOR LOGIC OR GATE SIMULATION BY: CHRISTIAN P. FEDERE A B OUT 1 1

10. TRANSISTOR LOGIC OR GATE SIMULATION BY: CHRISTIAN P. FEDERE A B OUT 1 1

11. TRANSISTOR LOGIC OR GATE SIMULATION BY: CHRISTIAN P. FEDERE A B OUT 1 1 1

12. TRANSISTOR LOGIC NAND GATE SIMULATION BY: CHRISTIAN P. FEDERE A B OUT 1 C D OUT 1 1

13. TRANSISTOR LOGIC NAND GATE SIMULATION BY: CHRISTIAN P. FEDERE A B OUT 1 1 C D OUT 1 1

14. TRANSISTOR LOGIC NOR GATE SIMULATION BY: CHRISTIAN P. FEDERE A B OUT 1 C D OUT 1

15. A4: SIMPLIFIED BOOLEAN EXPRESSION IMPLEMENTED USING UNIVERSAL LOGIC GATES SIMULATION BY: CHRISTIAN P. FEDERE