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1. Malaviya National Institute of Technology Jaipur Dr.C.Periasamy

2. Example: for below circuits (a) What is the total path effort from In to Out? (b) To minimize the delay, what should the EF/stage for this chain of gates be? (c) Size the gates in this chain to minimize the delay from In to Out.

3. Example: (a) What is the total path effort from In to Out? (b) To minimize the delay, what should the EF/stage for this chain of gates be? (c) Size the gates in this chain to minimize the delay from In to Out. Logical Effort(G) = g 1 •g 2 • g 3 • g 4 = 1 • 4/3 • 5/3 • 1 = 20/9 Electrical Effort(H) = C out / Cin = 10/2 = 5 Branching Effort(B) = b 1 • b 2 •b 3 • b 4 = 1 • 1 • 1•1 = 1 (a) Path Effort(F) = G H B = 20/9 • 5 • 1 = 100/9 (b) Best Stage Effort(f) = F 1/N =( 100/9) 1/4 =1.83 (c) Z= 10 C• 1/1.83 = 5.5C Y= 5.5 C • (5/3)/1.83 = 5C X=5C • (4/3)/1.83 = 3.62 C

4. Example: (a) What is the total path effort from In to Out? (b) To minimize the delay, what should the EF/stage for this chain of gates be? (c) Size the gates in this chain to minimize the delay from In to Out Logical Effort(G) = g 1 •g 2 • g 3 = 4/3 • 5/3 • 5/3 = 100/27 Electrical Effort(H) = C out / Cin = 45/8 = 5.625 Branching Effort(B) = b 1 • b 2 •b 3 = 1 • 3 •2 = 6 (a) Path Effort(F) = G H B = 100/27 • 6 • 5.625 = 125 (b) Best Stage Effort(f) = F 1/N =( 125) 1/3 = 5 (c) Y= 45 C • (5/3)/5 • 2 = 30 C X=30C • (5/3)/5 • 3 = 30C 8C = 30C • (4/3)/5 = 8C

5. What is the total path effort from In to Out? To minimize the delay, what should the EF/stage for this chain of gates be? Size the gates in this chain to minimize the delay from In to Out. d) Using this sizing, what is the delay (in units of tinv ) of your chain from In rising to Out falling? You can assume that the critical input of the complex gates is always at the “top” of the transistor stacks (i.e., the critical input is always closest to the output node), and that CD/CG = γ = 0.5. Example :

6. Example : Consider three alternative circuits for driving a load 25 times the input capacitance of the circuit. The first design uses one inverter, the second uses three inverters in series, and the third uses five in series. All three designs compute the same logic function. Which is best, and what is the minimum delay?

7. Example : Consider three alternative circuits for driving a load 25 times the input capacitance of the circuit. The first design uses one inverter, the second uses three inverters in series, and the third uses five in series. All three designs compute the same logic function. Which is best, and what is the minimum delay? The path logical effort is 1, the branching effort is 1, and the electrical effort is 25. path delay D = N( 25 ) 1 /N + N*p inv where N = 1, 3, or 5. For N = 1, D ˆ = 26 delay units; for N = 3, D ˆ = 11.8; N = 5, D ˆ = 14.5. The best choice is N = 3. In this design, each stage will bear an effort of ( 25 ) 1 / 3 = 2.9, so each inverter will be 2.9 times larger than its predecessor.

8. Example: Implementing an address decoder boils down to building an N-input AND gate. For this problem, we'll be looking at a hypothetical 4-input decoder. a) Draw the schematic of a 4-input AND implemented as a 4-input NAND followed by an inverter. What is the total LE of this implementation? b) Now draw the schematic of a 4-input AND implemented with 2 2-input NAND’s followed by a 2-input NOR. What is the total LE now? c) Finally, draw a 4-input AND implemented with 3 2-input NAND’s and 3 inverters and calculate the LE of this implementation. d) Assuming that the total LE of a 4-input AND is 2 and that the total load that this 4-input AND needs to drive is 128 times the input capacitance of the first stage, what is the optimal number of stages that should be used to minimize the delay?

9. LAB Exercise: Design and simulate function F = (AB+CD)’ using 0.5um technology with same L for all transistors. Assume that sizing an inverter with Wp = 2Wn makes tpHL equal to tpLH. a) Draw the schematic and spice net list for a static CMOS gate implementing the function. b) Do the appropriate sizing of each the transistor for tpHL=tpLH. Calculate the logical effort? c) Simulate the circuit using SPICE with sizing calculated in part b), plot the tp,avg of this gate vs. fan-out with input A transitioning and B=1, C=0, and D=1. Measure the delay at a fan-out of 1, 2, 3, and 4. d) Using the simulation results of part c) and a simulation of inverter delay vs fan-out, Calculate simulated logical effort and compare the result with the theatrical data obtained in part (b), Comment on the results?

10. Solution:

11. c) Plot in (d) SPICE Deck: * Homework 7 Problem 1d .LIB '/home/ff/ee141/MODELS/lib05um.txt * Function SUBCKT Definition .SUBCKT aoi22 vdd gnd a b c d out Mpa out a x vdd PMOS W=4u L=0.5u Mpb out b x vdd PMOS W=4u L=0.5u Mpc x c vdd vdd PMOS W=4u L=0.5u Mpd x d vdd vdd PMOS W=4u L=0.5u Mna out a y gnd NMOS W=2u L=0.5u Mnb y b gnd gnd NMOS W=2u L=0.5u Mnc out c z gnd NMOS W=2u L=0.5u Mnd z d gnd gnd NMOS W=2u L=0.5u .ENDS * Voltage Sources Vdd vdd 0 2.5V Vstep vstep 0 PULSE 0V 2.5V 10p 1p 1p 5n 10n * Applying Fanout .param fo = 1 xaoi1 vdd 0 vstep vdd gnd vdd vi aoi22 M=1 xaoi2 vdd 0 vi vdd gnd vdd vout aoi22 M='fo' xaoi3 vdd 0 vout vdd gnd vdd v3 aoi22 M='fo*fo' xaoi4 vdd 0 v3 vdd gnd vdd v4 aoi22 M='fo*fo*fo' * options .option post=2 nomod * analysis .TRAN 1PS 10NS sweep fo 1 4 1 .MEASURE TRAN tpHL TRIG V(vi) VAL=1.25V RISE=1 TARG V(vout) VAL=1.25V FALL=1 .MEASURE TRAN tpLH TRIG V(vi) VAL=1.25V FALL=1 TARG V(vout) VAL=1.25V RISE=1 .MEASURE TRAN tpavg PARAM='(tpHL+tpLH)/2' .END

12. d) SPICE Deck: . .LIB '/home/ff/ee141/MODELS/lib05um.txt * Inverter SUBCKT Definition .SUBCKT inv vdd gnd in out Mp out in vdd vdd PMOS W=2u L=0.5u Mn out in gnd gnd NMOS W=1u L=0.5u .ENDS * Voltage Sources V1 vdd 0 2.5V V2 vstep 0 PULSE 0V 2.5V 10p 1p 1p 5n 10n * Applying Fanout .param fo = 1 xinv1 vdd 0 vstep vi inv M=1 xinv2 vdd 0 vi vout inv M='fo' xinv3 vdd 0 vout v3 inv M='fo*fo' xinv4 vdd 0 v3 v4 inv M='fo*fo*fo' * options .option post=2 nomod * analysis .TRAN 1PS 10NS sweep fo 1 4 1 .MEASURE TRAN tpHL TRIG V(vi) VAL=1.25V RISE=1 TARG V(vout) VAL=1.25V FALL=1 .MEASURE TRAN tpLH TRIG V(vi) VAL=1.25V FALL=1 TARG V(vout) VAL=1.25V RISE=1 .MEASURE TRAN tpavg PARAM='(tpHL+tpLH)/2' .END

13. Mini Project Design and simulate a 5 stage ring-oscillator using 0.5um technology. Assume that sizing an inverter with Wp = 2Wn makes tpHL equal to tpLH. Estimate the actual rise and fall delay using SPICE simulation. (a) Check whether you are getting equal rise and fall, if not what P/N(Wp/ Wn) ratio gives equal delays? Run a bunch of simulation with different P/N size from range 4 to 16 with iteration of 30 and note down the optimum P/N. (b) Repeat process (a) i.e. P/N optimization for lowest average delay?

14. Thank You

15. Example Logical Effort(G) = g 1 •g 2 • g 3 • g 4 = 1 • 5/3 • 4/3 • 1 = 20/9 Electrical Effort(H) = C out / Cin = 20/10 = 2 Branching Effort(B) = b 1 • b 2 •b 3 • b 4 = 1 • 1 • 1•1 = 1 (a) Path Effort(F) = G H B = 20/9 • 2 • 1 = 40/9 (b) Best Stage Effort(f) = F 1/N =( 40/9) 1/4 =1.45 (c) Z= 20 C• 1/1.45 = 13.8 C Y= 13.8 C • (4/3)/1.45 = 12.68 C X= 12.68 C • (5/3)/1.45 = 14.57 C Delay(D) = (N • f + P) ts = 4 • 1.83 + (1+2+2+1) = 13.32 ts