LSSD Level-Sensitive Scan Design VLSI ECE 6th Sem

Is a design-for-testability (DFT) methodology used in VLSI (Very Large Scale Integration) design.
It's particularly effective for ensuring the testability of digital circuits, allowing for testing and debugging of integrated circuits (ICs).

1. LSSD (Level-Sensitive Scan Design) Is a design-for-testability (DFT) methodology used in VLSI (Very Large Scale Integration) design. It's particularly effective for ensuring the testability of digital circuits, allowing for testing and debugging of integrated circuits (ICs). LSSD scan latch is called : Shift Register Latch(SRL)

2. KEY CONCEPTS: Scan Design : Scan design converts flip-flops into scan flip-flops to make it easier to test digital circuits. Level-Sensitive : LSSD focuses on the circuit's state when the signal is high or low, not just when it changes. Shift registers : LSSD uses shift registers in test mode to input test patterns and output responses, helping detect circuit faults. Testability : LSSD aims to improve testing of complex VLSI circuits, It allows for the detection of faults that might be missed using traditional testing methods.

3. Shift register latches used in LSSD:

4. Explanation: Inputs : D, A, B are the data inputs to the latches. B0 This is a control input that determines the mode of operation Latches: 1. Master 2 port D-latch L1 2. Slave Latch L2 Outputs: 1. To system function: This is the output that goes to the normal system operation. 2. S0 : This is the scan output, which is used during the testing phase to shift out the data.

5. Normal Mode: When B is low, the circuit operates in normal mode. The data inputs (D0, C0, Sin, A0) are processed through the latches and sent to the system function.

6. Scan Mode : When B is high, the circuit operates in scan mode. The shift register captures the data from the inputs and shifts it through the latches (L1 and L2).