Machine language/nandtotetris/lecture_3
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About This Presentation
Explains how computer mammory(RAM, ROM) works uisng hack computer
Slide Content
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 1
Lecture 3
Memory
From Nand to Tetris
Building a Modern Computer from First Principles
These slides support chapter 3 of the book
The Elements of Computing Systems
By Noam Nisan and Shimon Schocken
MIT Press, 2021
Lecture 3
Memory
From Nand to Tetris
Building a Modern Computer from First Principles
These slides support chapter 3 of the book
The Elements of Computing Systems
By Noam Nisan and Shimon Schocken
MIT Press, 2021
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 2
Nand to Tetris Roadmap: Hardware
assembler
Nand
hardware platformabstraction
computerabstraction
ALU, RAMabstraction
elementary
logic gates
building a
computerbuilding
chipsbuilding
gates
p2p3
p1
p5p4
abstraction
machine
language
p6
Nand to Tetris Roadmap: Hardware
assembler
Nand
hardware platformabstraction
computerabstraction
ALU, RAMabstraction
elementary
logic gates
building a
computerbuilding
chipsbuilding
gates
p2p3
p1
p5p4
abstraction
machine
language
p6
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 3
Nand to Tetris Roadmap: Hardware
assembler
Nand
hardware platformabstraction
computerabstraction
ALU, RAMabstraction
elementary
logic gates
building a
computerbuilding
chipsbuilding
gates
p2p3
p1
p5p4
abstraction
machine
language
p6
Project 1: Build basic logic gates
Project 2: Build the ALU
Nand to Tetris Roadmap: Hardware
assembler
Nand
hardware platformabstraction
computerabstraction
ALU, RAMabstraction
elementary
logic gates
building a
computerbuilding
chipsbuilding
gates
p2p3
p1
p5p4
abstraction
machine
language
p6
Project 1: Build basic logic gates
Project 2: Build the ALU
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 4
Nand to Tetris Roadmap: Hardware
assembler
Nand
hardware platformabstraction
computerabstraction
ALU, RAMabstraction
elementary
logic gates
building a
computerbuilding
chipsbuilding
gates
p3
p5p4
abstraction
machine
language
p6
This lecture / project 3:
Build the computer’s memory system
Project 1: Build basic logic gates
Project 2: Build the ALU
p2
p1
Nand to Tetris Roadmap: Hardware
assembler
Nand
hardware platformabstraction
computerabstraction
ALU, RAMabstraction
elementary
logic gates
building a
computerbuilding
chipsbuilding
gates
p3
p5p4
abstraction
machine
language
p6
This lecture / project 3:
Build the computer’s memory system
Project 1: Build basic logic gates
Project 2: Build the ALU
p2
p1
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 5
Combinational logic
The type of digital logic used for building all the gates and chips
that we saw so far:
•The chip’s current inputs are just “sitting there” –fixed and unchanging
•The chip’s output is a function (“combination”) of the current inputs,
and the current inputs only
This type of digital logic is called:
qCombinational logic
qTime-independent logicALU
+
0101
1000
1101
ALU: The “topmost”
combinational chip
Combinational logic
The type of digital logic used for building all the gates and chips
that we saw so far:
•The chip’s current inputs are just “sitting there” –fixed and unchanging
•The chip’s output is a function (“combination”) of the current inputs,
and the current inputs only
This type of digital logic is called:
qCombinational logic
qTime-independent logicALU
+
0101
1000
1101
ALU: The “topmost”
combinational chip
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 6
Hello, time
Software needs
x = 17
Example (variables)
for i in range(0, 10):
print(i)
Example (iteration)
•The hardware must handle
the physical time delays
associated with moving and
computing data
Hardware needs
•The hardware must be able to
remember things, over time:
•The hardware must be able to do
things, one at a time (sequentially):
Hello, time
Software needs
x = 17
Example (variables)
for i in range(0, 10):
print(i)
Example (iteration)
•The hardware must handle
the physical time delays
associated with moving and
computing data
Hardware needs
•The hardware must be able to
remember things, over time:
•The hardware must be able to do
things, one at a time (sequentially):
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 7
Hello, time
•The hardware must handle
the physical time delays
associated with moving and
computing data
Hardware needs
ALU
+
5
8
13Now compute
7 + 11 ...
It will take some time before 7 and 11 will settle down in
the input pins, and before the sum 7 + 11 will stabilize.
Till then, the ALU will output nonsense.
Software needs
x = 17
Example (variables):
for i in range(0, 10):
print(i)
Example (iteration):
•The hardware must be able to
remember things, over time:
•The hardware must be able to do
things, one at a time (sequentially):
Hello, time
•The hardware must handle
the physical time delays
associated with moving and
computing data
Hardware needs
ALU
+
5
8
13Now compute
7 + 11 ...
It will take some time before 7 and 11 will settle down in
the input pins, and before the sum 7 + 11 will stabilize.
Till then, the ALU will output nonsense.
Software needs
x = 17
Example (variables):
for i in range(0, 10):
print(i)
Example (iteration):
•The hardware must be able to
remember things, over time:
•The hardware must be able to do
things, one at a time (sequentially):
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 8
Hello, time
•Design decision: Set the cycle length to be slightly > than the maximum time delay
•Observe / use the chips' outputs only at the end of cycles (time-steps),
ignoring what happens within cycles
•Details later.
cycle length
Chip’s input:
Chip’s output:
Clock:tick
tockClock:
a
f(a)
b
f(b)
c
f(c)
d
f(d)
e
f(e)
time-step:
In addition:
The consideration
of time enables the
implementation of
chips that can
“remember” values.
Solution: Neutralize the time delays by using discrete time
Hello, time
•Design decision: Set the cycle length to be slightly > than the maximum time delay
•Observe / use the chips' outputs only at the end of cycles (time-steps),
ignoring what happens within cycles
•Details later.
cycle length
Chip’s input:
Chip’s output:
Clock:tick
tockClock:
a
f(a)
b
f(b)
c
f(c)
d
f(d)
e
f(e)
time-step:
In addition:
The consideration
of time enables the
implementation of
chips that can
“remember” values.
Solution: Neutralize the time delays by using discrete time
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 9
Memory
Memory is time-based:
We remember now what was
committed to memory earlier.
9
Memory:The faculty of the brain by
which data or information is encoded,
stored, and retrieved when needed.
It is the retention of information over
time for the purpose of influencing
future action (Wikipedia)
Memory
Memory is time-based:
We remember now what was
committed to memory earlier.
9
Memory:The faculty of the brain by
which data or information is encoded,
stored, and retrieved when needed.
It is the retention of information over
time for the purpose of influencing
future action (Wikipedia)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 10
Memory
loading
x = 21
(cycles)
1 2 3 4 5 6 7 100 101 102 103 104 105 106 ...time...
loading
x = 17
storing
, 17, 17, 17, 17, 17, 17, ... ,
storing
, 21, 21, 21, 21, 21, 21, ...
The challenge: Building chips that realize this functionality,
i.e. chips designed to maintain state and change state.
Basic operations
•“Loading” a value
•“Storing” a value
Register
in out
load
Memory
loading
x = 21
(cycles)
1 2 3 4 5 6 7 100 101 102 103 104 105 106 ...time...
loading
x = 17
storing
, 17, 17, 17, 17, 17, 17, ... ,
storing
, 21, 21, 21, 21, 21, 21, ...
The challenge: Building chips that realize this functionality,
i.e. chips designed to maintain state and change state.
Basic operations
•“Loading” a value
•“Storing” a value
Register
in out
load
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 11
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 12
Representing time
1
0clock:
time: 1 2 3 4 5 . . .
physical
time:
Arrow of time:
Continuous
Discrete time
Design decision:
Track state changes only
when advancing from
one time-step to another
Representing time
1
0clock:
time: 1 2 3 4 5 . . .
physical
time:
Arrow of time:
Continuous
Discrete time
Design decision:
Track state changes only
when advancing from
one time-step to another
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 13
Chip behavior over time(example: Not gate)
1
0
0
1
clock:
time: 1 2 3 4 5 . . .
0
1
physical
time:
(example)
Desired / idealized behavior of the in and out signals:
That’s how we want the hardware to behave
Arrow of time:
Continuous
Discrete time
Design decision:
Track state changes only
when advancing from
one time-step to another
out:
Not(in)
in:
(examples
of arbitrary
values)
Chip behavior over time(example: Not gate)
1
0
0
1
clock:
time: 1 2 3 4 5 . . .
0
1
physical
time:
(example)
Desired / idealized behavior of the in and out signals:
That’s how we want the hardware to behave
Arrow of time:
Continuous
Discrete time
Design decision:
Track state changes only
when advancing from
one time-step to another
out:
Not(in)
in:
(examples
of arbitrary
values)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 14
Chip behavior over time(example: Not gate)
1
0
0
1
clock:
time: 1 2 3 4 5 . . .
0
1
physical
time:
(example)
Arrow of time:
Continuous
Actual behavior of the in and out signals:
Influenced by physical time delays
Discrete time
Design decision:
Track state changes only
when advancing from
one time-step to another
out:
Not(in)
in:
(examples
of arbitrary
values)
Chip behavior over time(example: Not gate)
1
0
0
1
clock:
time: 1 2 3 4 5 . . .
0
1
physical
time:
(example)
Arrow of time:
Continuous
Actual behavior of the in and out signals:
Influenced by physical time delays
Discrete time
Design decision:
Track state changes only
when advancing from
one time-step to another
out:
Not(in)
in:
(examples
of arbitrary
values)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 15
Chip behavior over time(example: Not gate)
1
0
0
1
clock:
time: 1 2 3 4 5 . . .
0
1
physical
time:
(example)
Time delays
•Propagation delays
•Computation delays
Arrow of time:
Continuous
Discrete time
Design decision:
Track state changes only
when advancing from
one time-step to another
out:
Not(in)
in:
(examples
of arbitrary
values)
Cycle length
•Design parameter
•Set to be slightly > max(time delays)
Chip behavior over time(example: Not gate)
1
0
0
1
clock:
time: 1 2 3 4 5 . . .
0
1
physical
time:
(example)
Time delays
•Propagation delays
•Computation delays
Arrow of time:
Continuous
Discrete time
Design decision:
Track state changes only
when advancing from
one time-step to another
out:
Not(in)
in:
(examples
of arbitrary
values)
Cycle length
•Design parameter
•Set to be slightly > max(time delays)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 16
Chip behavior over time(example: Not gate)
1
0
0
1
clock:
time: 1 2 3 4 5 . . .
0
1
physical
time:
Resulting effect
Since we track state changes only at cycle ends,
Combinational chips (like Not) react “immediately” to their inputs.
out:
Not(in)
(example)
in:
(examples
of arbitrary
values)
Arrow of time:
Continuous
Discrete time
Design decision:
Track state changes only
when advancing from
one time-step to another
Chip behavior over time(example: Not gate)
1
0
0
1
clock:
time: 1 2 3 4 5 . . .
0
1
physical
time:
Resulting effect
Since we track state changes only at cycle ends,
Combinational chips (like Not) react “immediately” to their inputs.
out:
Not(in)
(example)
in:
(examples
of arbitrary
values)
Arrow of time:
Continuous
Discrete time
Design decision:
Track state changes only
when advancing from
one time-step to another
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 17
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 18
Clock
Clock
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 19
Clock: Simulated implementation
Interactive simulation
A clock icon, used to generate a
sequence of tick-tock signals:
0, 0+, 1, 1+, 2, 2+, 3, 3+, ...
Clock: Simulated implementation
Interactive simulation
A clock icon, used to generate a
sequence of tick-tock signals:
0, 0+, 1, 1+, 2, 2+, 3, 3+, ...
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 20
Clock: Simulated implementation
...
// Sets inputs, advances the clock, and
// writes output values as it goes along.
set in 19,
set load 1,
tick,
output,
tock,
output,
tick, tock,
output,
...
Script-based simulation
“tick” and “tock” commands,
used to advance the clock:
Interactive simulation
A clock icon, used to generate a
sequence of tick-tock signals:
0, 0+, 1, 1+, 2, 2+, 3, 3+, ...
Clock: Simulated implementation
...
// Sets inputs, advances the clock, and
// writes output values as it goes along.
set in 19,
set load 1,
tick,
output,
tock,
output,
tick, tock,
output,
...
Script-based simulation
“tick” and “tock” commands,
used to advance the clock:
Interactive simulation
A clock icon, used to generate a
sequence of tick-tock signals:
0, 0+, 1, 1+, 2, 2+, 3, 3+, ...
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 21
Clock: Physical implementation
Physical clock
An oscillator is used to deliver an ongoing train of “tick/tock” signals
“1 MHz electronic oscillator circuit uses the resonant properties of an internal quartz
crystal to control the frequency. Provides the clock signal for digital devices such as
computers.” (Wikipedia)
tick/tock
signal
(Chip diagram convention:
A triangle icon represents a clock signal input)
Clock: Physical implementation
Physical clock
An oscillator is used to deliver an ongoing train of “tick/tock” signals
“1 MHz electronic oscillator circuit uses the resonant properties of an internal quartz
crystal to control the frequency. Provides the clock signal for digital devices such as
computers.” (Wikipedia)
tick/tock
signal
(Chip diagram convention:
A triangle icon represents a clock signal input)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 22
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 23
Input
Registers
Memory
(many
registers)Output
CPU
Registers
ALU
Computer Architecture
(a few)
Input
Registers
Memory
(many
registers)Output
CPU
Registers
ALU
Computer Architecture
(a few)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 24
Registers
Designed to:
•“Store” a value , until...
•“Loaded” with a new value
outin
load
Bit
1-bit register
Register
in
w
out
w
load
multi-bit register
x = 17, 17, 17, 17, 17, 17, 17, 17, ..., 17
x = 21, 21, 21, 21, 21, 21, ..., 21
time:
loadingstoring
loadingstoring
Registers
Designed to:
•“Store” a value , until...
•“Loaded” with a new value
outin
load
Bit
1-bit register
Register
in
w
out
w
load
multi-bit register
x = 17, 17, 17, 17, 17, 17, 17, 17, ..., 17
x = 21, 21, 21, 21, 21, 21, ..., 21
time:
loadingstoring
loadingstoring
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 25
1-Bit register
out:
in:
load:
0
1
0
1
1
0
time:12345678
“storing”“storing”“loading”“loading”Resulting behavior:
outin
load
Bit
examples
of arbitrary
input values
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
1-Bit register
out:
in:
load:
0
1
0
1
1
0
time:12345678
“storing”“storing”“loading”“loading”Resulting behavior:
outin
load
Bit
examples
of arbitrary
input values
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 26
1-Bit register
To read:
probe out(out always emits the register’s state)
To write:
set in = v
set load = 1
Result: The register’s state becomes v;
From the next time-step onward, out will emit v,
until the next load.
outin
load
Bit
Usage:
Best practice: After writing, set load to 0
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
1-Bit register
To read:
probe out(out always emits the register’s state)
To write:
set in = v
set load = 1
Result: The register’s state becomes v;
From the next time-step onward, out will emit v,
until the next load.
outin
load
Bit
Usage:
Best practice: After writing, set load to 0
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 27
Multi-bit register
Register
in
w
out
w
load
Load / store behavior: Exactly the same as a 1-bit register
Read / write usage: Exactly the same as a 1-bit register
We’ll focus on bit width w = 16,
without loss of generality
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
Multi-bit register
Register
in
w
out
w
load
Load / store behavior: Exactly the same as a 1-bit register
Read / write usage: Exactly the same as a 1-bit register
We’ll focus on bit width w = 16,
without loss of generality
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 28
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 29
Input
Computer architecture
Memory
(RAM) Output
CPU
Registers
ALU
Input
Computer architecture
Memory
(RAM) Output
CPU
Registers
ALU
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 30
RAM
Abstraction: A sequence ofn addressable, w-bit registers
Word width: Typically w = 16, 32, 64, 128 bits (Hack computer: w = 16)
Register0
1
n-1
...
RAMn
Register
Register
RAM
Abstraction: A sequence ofn addressable, w-bit registers
Word width: Typically w = 16, 32, 64, 128 bits (Hack computer: w = 16)
Register0
1
n-1
...
RAMn
Register
Register
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 31
RAM
Suppose that the RAM size is n
(for example, n = 8 registers);
What should be the value of k?
k = log2n
out
in
load
w
Register0
1
n-1
...
RAMn
Register
Register
address
k
w
Abstraction: A sequence ofn addressable, w-bit registers
Word width: Typically w = 16, 32, 64, 128 bits (Hack computer: w = 16)
RAM
Suppose that the RAM size is n
(for example, n = 8 registers);
What should be the value of k?
k = log2n
out
in
load
w
Register0
1
n-1
...
RAMn
Register
Register
address
k
w
Abstraction: A sequence ofn addressable, w-bit registers
Word width: Typically w = 16, 32, 64, 128 bits (Hack computer: w = 16)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 32
RAM
If load == 0, the RAM maintains its state
If load == 1, RAM[address] is set to the value of in
The loaded value will be emitted by out from the
next time-step (cycle) onward
out
in
load
w
Register0
1
n-1
...
RAMn
Register
Register
address
k
(Only one RAM register is selected;
All the other registers are not affected)
(out always emits
the value of RAM[i])
Usage
To read register i :
set address = i,
probe out
To write v in register i :
set address = i,
set in = v,
set load = 1
Result: RAM[i] ← v
From the next time-step onward out will emit v
Behavior
w
RAM
If load == 0, the RAM maintains its state
If load == 1, RAM[address] is set to the value of in
The loaded value will be emitted by out from the
next time-step (cycle) onward
out
in
load
w
Register0
1
n-1
...
RAMn
Register
Register
address
k
(Only one RAM register is selected;
All the other registers are not affected)
(out always emits
the value of RAM[i])
Usage
To read register i :
set address = i,
probe out
To write v in register i :
set address = i,
set in = v,
set load = 1
Result: RAM[i] ← v
From the next time-step onward out will emit v
Behavior
w
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 33
RAM
Why “Random Access Memory”?
Irrespective of the RAM size (n),
any randomly selected register can
be accessed “instantaneously”,
in one time cycle.
out
in
load
w
Register0
1
n-1
...
RAMn
Register
Register
address
k
w
RAM
Why “Random Access Memory”?
Irrespective of the RAM size (n),
any randomly selected register can
be accessed “instantaneously”,
in one time cycle.
out
in
load
w
Register0
1
n-1
...
RAMn
Register
Register
address
k
w
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 34
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 35
Input
Computer architecture
MemoryOutput
CPU
Registers
ALU
One of the CPU
registers acts as a
“program counter”
Input
Computer architecture
MemoryOutput
CPU
Registers
ALU
One of the CPU
registers acts as a
“program counter”
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 36
Counter
PC = 0
PC = n
facilitates fetching the first instruction
facilitates “jumping to”, and fetching, some instruction
PC++facilitates fetching the next instruction
•The computer (that we will build later in the course) needs to keep
track of which instruction should be fetched and executed next
•This is done using a register typically called ProgramCounter
•The PCis used to store the address of the instruction that should be
fetched and executed next
Basic PCoperations
increment:
qload:
qreset:
Counter
PC = 0
PC = n
facilitates fetching the first instruction
facilitates “jumping to”, and fetching, some instruction
PC++facilitates fetching the next instruction
•The computer (that we will build later in the course) needs to keep
track of which instruction should be fetched and executed next
•This is done using a register typically called ProgramCounter
•The PCis used to store the address of the instruction that should be
fetched and executed next
Basic PCoperations
increment:
qload:
qreset:
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 37
Counter
To read:
probe out
To reset:
assert reset,
set the other control bits to 0
To increment:
assert inc,
set the other control bits to 0
To load:
set in to v,
assert load,
set the other control bits to 0
Usage:
if reset(t): out(t + 1) = 0
else if load(t): out(t + 1) = in(t)
else if inc(t): out(t + 1) = out(t) + 1
else out(t + 1) = out(t)
in
16
out
16
resetloadinc
PC
Counter
To read:
probe out
To reset:
assert reset,
set the other control bits to 0
To increment:
assert inc,
set the other control bits to 0
To load:
set in to v,
assert load,
set the other control bits to 0
Usage:
if reset(t): out(t + 1) = 0
else if load(t): out(t + 1) = in(t)
else if inc(t): out(t + 1) = out(t) + 1
else out(t + 1) = out(t)
in
16
out
16
resetloadinc
PC
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 38
Recap: Combinational logic / Sequential logic
Combinational logic
Sequential logic
The output depends
on current inputs only
The clock is used to
stabilize outputs
f(a,b)f(b,c)f(c,d)f(d,e)
The output depends on:
•Previous inputs
•And, optionally, also on
current inputs
Used for building memory
chips (registers, RAM)
Recap: Combinational logic / Sequential logic
Combinational logic
Sequential logic
The output depends
on current inputs only
The clock is used to
stabilize outputs
f(a,b)f(b,c)f(c,d)f(d,e)
The output depends on:
•Previous inputs
•And, optionally, also on
current inputs
Used for building memory
chips (registers, RAM)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 39
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 40
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 41
DFF
12345678
0
1
1
0
time:
in:
out:
How can we “load” and then “maintain” a value (0 or 1) over time,
without having to feed the value in every cycle?
Data Flip Flop (aka latch)
The most elementary sequential
gate: Outputs the input in the
previous time-step
DFF
outin out(t + 1) = in(t)
examples
of arbitrary
inputs
DFF
12345678
0
1
1
0
time:
in:
out:
How can we “load” and then “maintain” a value (0 or 1) over time,
without having to feed the value in every cycle?
Data Flip Flop (aka latch)
The most elementary sequential
gate: Outputs the input in the
previous time-step
DFF
outin out(t + 1) = in(t)
examples
of arbitrary
inputs
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 42
From DFF to a 1-Bit register
We have to realize a “loading” behavior and a ”storing” behavior,
and be able to select between these two states
DFF
outin
From DFF to a 1-Bit register
We have to realize a “loading” behavior and a ”storing” behavior,
and be able to select between these two states
DFF
outin
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 43
From DFF to a 1-Bit register
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
outin
load
DFFMux
out (of the DFF)
Behavior
if load == 1 the register’s value becomes in
else the register maintains its current value
We have to realize a “loading” behavior and a ”storing” behavior,
and be able to select between these two states
1-bit register
Stores one bit
over time
From DFF to a 1-Bit register
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
outin
load
DFFMux
out (of the DFF)
Behavior
if load == 1 the register’s value becomes in
else the register maintains its current value
We have to realize a “loading” behavior and a ”storing” behavior,
and be able to select between these two states
1-bit register
Stores one bit
over time
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 44
Register
Behavior
if load == 1 the register’s value becomes in
else the register maintains its current value
outin
load
Bit
1-bit register
Stores one bit
over time
zoom out...
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
Register
Behavior
if load == 1 the register’s value becomes in
else the register maintains its current value
outin
load
Bit
1-bit register
Stores one bit
over time
zoom out...
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 45
Register
load
outin1-bit register
Stores one bit
over time
Behavior
if load == 1 the register’s value becomes in
else the register maintains its current value
w
out
load
w
in
...w-bit register
Stores w bits
over time
BitBitBitBitw 1-bit registers
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
Register
load
outin1-bit register
Stores one bit
over time
Behavior
if load == 1 the register’s value becomes in
else the register maintains its current value
w
out
load
w
in
...w-bit register
Stores w bits
over time
BitBitBitBitw 1-bit registers
if load(t):
out(t + 1) = in(t)
else
out(t + 1) = out(t)
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 46
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 47
From DFF to RAM
47
1-bit
register
Bit
Data
Flip-Flop
DFF
0
1
n-1
...
Register
Random Access Memory
RAMn
Register
Register
16-bit register
...
Register
BitBitBit?DFF
From DFF to RAM
47
1-bit
register
Bit
Data
Flip-Flop
DFF
0
1
n-1
...
Register
Random Access Memory
RAMn
Register
Register
16-bit register
...
Register
BitBitBit?DFF
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 48
From DFF to RAM
48
1-bit
register
Bit
Data
Flip-Flop
DFF
0
1
n-1
...
Register
RAMn
Register
Register
16-bit register
...
Register
BitBitBit?DFF
Random Access Memory
From DFF to RAM
48
1-bit
register
Bit
Data
Flip-Flop
DFF
0
1
n-1
...
Register
RAMn
Register
Register
16-bit register
...
Register
BitBitBit?DFF
Random Access Memory
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 49
RAM: Abstraction
(out always emits the state of RAM[i])
Usage:To read register i :
set address = i,
probe out
To write v in register i :
set address = i,
set in = v,
set load = 1
Result: RAM[i] ← v
From the next time-step onward, out emits v
RAM of n
registers:
RAM: Abstraction
(out always emits the state of RAM[i])
Usage:To read register i :
set address = i,
probe out
To write v in register i :
set address = i,
set in = v,
set load = 1
Result: RAM[i] ← v
From the next time-step onward, out emits v
RAM of n
registers:
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 50
RAM: Implementation
DMux
(1 to n)
Register
in
w
load
out
w
Register
in
w
load
out
w
Register
in
w
load
out
w
...
Mux
(n to 1)
out
w
in
w
address
k
load
RAM of n
registers:
Partial diagram,
showing some of
the chip-parts,
without
connections
Reading: Can be realized using a Mux
Writing: Can be realized using a DMux
Connections?
You figure it out
RAM: Implementation
DMux
(1 to n)
Register
in
w
load
out
w
Register
in
w
load
out
w
Register
in
w
load
out
w
...
Mux
(n to 1)
out
w
in
w
address
k
load
RAM of n
registers:
Partial diagram,
showing some of
the chip-parts,
without
connections
Reading: Can be realized using a Mux
Writing: Can be realized using a DMux
Connections?
You figure it out
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 51
RAM: Implementation
DMux
(1 to n)
Register
in
w
load
out
w
Register
in
w
load
out
w
Register
in
w
load
out
w
...
Mux
(n to 1)
How the magic of direct access works
•Like every memory chip, the storage behavior is based on sequential logic
•But, the addressing is realized by the Mux / DMux chips, which are combinational.
out
w
in
w
address
k
load
RAM of n
registers:
Partial diagram,
showing some of
the chip-parts,
without
connections
RAM: Implementation
DMux
(1 to n)
Register
in
w
load
out
w
Register
in
w
load
out
w
Register
in
w
load
out
w
...
Mux
(n to 1)
How the magic of direct access works
•Like every memory chip, the storage behavior is based on sequential logic
•But, the addressing is realized by the Mux / DMux chips, which are combinational.
out
w
in
w
address
k
load
RAM of n
registers:
Partial diagram,
showing some of
the chip-parts,
without
connections
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 52
RAM: Implementation
...
RAM8
Register
Register
Register
...
RAM64
RAM8
RAM8
RAM8
Same technique can be
used to implement RAM
devices of any size
…
...
RAM512
RAM64
RAM64
RAM64
RAM: Implementation
...
RAM8
Register
Register
Register
...
RAM64
RAM8
RAM8
RAM8
Same technique can be
used to implement RAM
devices of any size
…
...
RAM512
RAM64
RAM64
RAM64
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 53
RAM: Implementation
chip namenk
RAM883
RAM64646
RAM5125129
RAM4K409612
RAM16K1638414
Why stop at RAM16K?
Because that’s what we need for
building the Hack computer.
out
in
load
16
Register0
1
n-1
...
RAMn
Register
Register
address
k
16
A family of 16-bit RAM chips:
RAM: Implementation
chip namenk
RAM883
RAM64646
RAM5125129
RAM4K409612
RAM16K1638414
Why stop at RAM16K?
Because that’s what we need for
building the Hack computer.
out
in
load
16
Register0
1
n-1
...
RAMn
Register
Register
address
k
16
A family of 16-bit RAM chips:
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 54
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Chapter 3: Memory
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 55
Project 3
Given:
•All the chips built in projects 1 and 2
•Data Flip-Flop (built-in DFF gate)
Build:
•Bit
•Register
•PC
•RAM8
•RAM64
•RAM512
•RAM4K
•RAM16K
Why is the DFF built-in?
Project 3
Given:
•All the chips built in projects 1 and 2
•Data Flip-Flop (built-in DFF gate)
Build:
•Bit
•Register
•PC
•RAM8
•RAM64
•RAM512
•RAM4K
•RAM16K
Why is the DFF built-in?
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 56
DFF implementation
•A DFF gate can be built by connecting Nand gates with
feedback loops
•The resulting implementation is elegant, yet impossible to
realize on the supplied hardware simulator:
•Our hardware simulator does not allow loops of
combinational chips (like Nand)
•Instead, we use a built-in DFF implementation:
/** Data Flip-flop: out(t) = in(t – 1)
* where t is the current time unit. */
CHIP DFF {
IN in;
OUT out;
BUILTIN DFF;
CLOCKED in;
}
Part of a possible
DFF implementation
Implementation note
HDL-wise, we need the DFF as a chip-part
in one chip only: Bit
All the other memory chips are built on
top of Bit.
DFF implementation
•A DFF gate can be built by connecting Nand gates with
feedback loops
•The resulting implementation is elegant, yet impossible to
realize on the supplied hardware simulator:
•Our hardware simulator does not allow loops of
combinational chips (like Nand)
•Instead, we use a built-in DFF implementation:
/** Data Flip-flop: out(t) = in(t – 1)
* where t is the current time unit. */
CHIP DFF {
IN in;
OUT out;
BUILTIN DFF;
CLOCKED in;
}
Part of a possible
DFF implementation
Implementation note
HDL-wise, we need the DFF as a chip-part
in one chip only: Bit
All the other memory chips are built on
top of Bit.
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 57
Project 3
Given:
•All the chips built in projects 1 and 2
•Data Flip-Flop (built-in DFF gate)
Build:
•Bit
•Register
•PC
•RAM8
•RAM64
•RAM512
•RAM4K
•RAM16K
Project 3
Given:
•All the chips built in projects 1 and 2
•Data Flip-Flop (built-in DFF gate)
Build:
•Bit
•Register
•PC
•RAM8
•RAM64
•RAM512
•RAM4K
•RAM16K
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 58
1-Bit register
outin
load
Bit
Bit.hdl
Implementation tip
Realize the diagram
outin
load
DFFMux
out (of the DFF)
/** 1-bit register:
if load(t ): out(t + 1) = in(t)
else out(t + 1) = out(t)
*/
CHIP Bit {
IN in, load;
OUT out;
PARTS:
//// Replace with your code
}
1-Bit register
outin
load
Bit
Bit.hdl
Implementation tip
Realize the diagram
outin
load
DFFMux
out (of the DFF)
/** 1-bit register:
if load(t ): out(t + 1) = in(t)
else out(t + 1) = out(t)
*/
CHIP Bit {
IN in, load;
OUT out;
PARTS:
//// Replace with your code
}
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 59
16-bit Register
Register.hdl
Register
in
16
out
16
load
Implementation tip
Realize the diagram
Partial diagram, showing chip-parts without connections
...BitBitBitBitin
16
out
16
load
/** 16-bit register:
if load(t ): out(t + 1) = in(t)
else out(t + 1) = out(t)
*/
CHIP Register {
IN in[16], load;
OUT out[16];
PARTS:
//// Replace with your code
}
16-bit Register
Register.hdl
Register
in
16
out
16
load
Implementation tip
Realize the diagram
Partial diagram, showing chip-parts without connections
...BitBitBitBitin
16
out
16
load
/** 16-bit register:
if load(t ): out(t + 1) = in(t)
else out(t + 1) = out(t)
*/
CHIP Register {
IN in[16], load;
OUT out[16];
PARTS:
//// Replace with your code
}
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 60
16-bit Counter
Implementation notes
•Can be built using the following chip-parts: Register, Inc16, Mux16
•Tip: The value of an internal pin can simultaneously feed the input pins of several chips
•Recommendation:
Start by building a basic PC chip that has one mode and one control bit only: inc;
Next, extend your design and HDL code to handle the load bit, and the reset bit.
/**
16-bit counter:
if reset(t): out(t + 1) = 0
else if load(t): out(t + 1) = in(t)
else if inc(t): out(t + 1) = out(t) + 1
else out(t + 1) = out(t)
*/
CHIP PC {
IN in[16], load, inc, reset;
OUT out[16];
PARTS:
//// Replace with your code
}
in
16
out
16
resetloadinc
PC
PC.hdl
16-bit Counter
Implementation notes
•Can be built using the following chip-parts: Register, Inc16, Mux16
•Tip: The value of an internal pin can simultaneously feed the input pins of several chips
•Recommendation:
Start by building a basic PC chip that has one mode and one control bit only: inc;
Next, extend your design and HDL code to handle the load bit, and the reset bit.
/**
16-bit counter:
if reset(t): out(t + 1) = 0
else if load(t): out(t + 1) = in(t)
else if inc(t): out(t + 1) = out(t) + 1
else out(t + 1) = out(t)
*/
CHIP PC {
IN in[16], load, inc, reset;
OUT out[16];
PARTS:
//// Replace with your code
}
in
16
out
16
resetloadinc
PC
PC.hdl
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 61
Project 3
Given
•All the chips built in projects 1 and 2
•Data Flip-Flop (built-in DFF gate)
Build the following chips
•Bit
•Register
•PC
•RAM8
•RAM64
•RAM512
•RAM4K
•RAM16K
Project 3
Given
•All the chips built in projects 1 and 2
•Data Flip-Flop (built-in DFF gate)
Build the following chips
•Bit
•Register
•PC
•RAM8
•RAM64
•RAM512
•RAM4K
•RAM16K
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 62
8-Register RAM
/* Memory of 8 registers, each 16 bit-wide.
out holds the valuestored at the memory location
specified by address. If load==1, then the in value
is loaded into the memory location specified by
address (the loaded value will appear in out from
the next time step onward).
*/
CHIP RAM8 {
IN in[16], load, address[3];
OUT out[16];
PARTS:
//// Replace with your code
}
RAM8.hdl
out
in
load
Register
...
RAMn
Register
Register
address
3
16
16
8-Register RAM
/* Memory of 8 registers, each 16 bit-wide.
out holds the valuestored at the memory location
specified by address. If load==1, then the in value
is loaded into the memory location specified by
address (the loaded value will appear in out from
the next time step onward).
*/
CHIP RAM8 {
IN in[16], load, address[3];
OUT out[16];
PARTS:
//// Replace with your code
}
RAM8.hdl
out
in
load
Register
...
RAMn
Register
Register
address
3
16
16
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 63
8-Register RAM
DMux
(1 to 8)
Register
in
16
load
out
Register
in
load
out
Register
in
load
out
...
Mux
(8 to 1)
out
16
in
16
address
3
load
Partial diagram, showing some of the chip-parts, without connections
Implementation tip
Figure out the missing connections, and realize the diagram.
16
16
16
16
16
8-Register RAM
DMux
(1 to 8)
Register
in
16
load
out
Register
in
load
out
Register
in
load
out
...
Mux
(8 to 1)
out
16
in
16
address
3
load
Partial diagram, showing some of the chip-parts, without connections
Implementation tip
Figure out the missing connections, and realize the diagram.
16
16
16
16
16
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 64
Project 3
Given
•All the chips built in projects 1 and 2
•Data Flip-Flop (built-in DFF gate)
A family of RAM chips
Build the following chips
•Bit
•Register
•PC
•RAM8
•RAM64
•RAM512
•RAM4K
•RAM16K
Project 3
Given
•All the chips built in projects 1 and 2
•Data Flip-Flop (built-in DFF gate)
A family of RAM chips
Build the following chips
•Bit
•Register
•PC
•RAM8
•RAM64
•RAM512
•RAM4K
•RAM16K
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 65
out
in
load
16
Register
...
RAMn
Register
Register
address
k
16
n-Register RAM
RAMn.hdl
/* Memory of n registers, each 16 bit-wide.
out holds the valuestored at the memory location
specified by address. If load==1, then the in value
is loaded into the memory location specified by
address (the loaded value will appear in out from
the next time step onward).
*/
CHIP RAMn {
IN in[16], load, address[k];
OUT out[16];
PARTS:
//// Replace with your code
}
out
in
load
16
Register
...
RAMn
Register
Register
address
k
16
n-Register RAM
RAMn.hdl
/* Memory of n registers, each 16 bit-wide.
out holds the valuestored at the memory location
specified by address. If load==1, then the in value
is loaded into the memory location specified by
address (the loaded value will appear in out from
the next time step onward).
*/
CHIP RAMn {
IN in[16], load, address[k];
OUT out[16];
PARTS:
//// Replace with your code
}
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 66
chip namenk
RAM883
RAM64646
RAM5125129
RAM4K409612
RAM16K1638414
out
in
load
16
Register
...
RAMn
Register
Register
address
k
16
n-Register RAM
Implementation tips
•Think about the RAM’s address input
as consisting of two fields:
–One field selects a RAM-part;
–The other field selects a register
within that RAM-part
•Use logic gates to effect this
addressing scheme
chip namenk
RAM883
RAM64646
RAM5125129
RAM4K409612
RAM16K1638414
out
in
load
16
Register
...
RAMn
Register
Register
address
k
16
n-Register RAM
Implementation tips
•Think about the RAM’s address input
as consisting of two fields:
–One field selects a RAM-part;
–The other field selects a register
within that RAM-part
•Use logic gates to effect this
addressing scheme
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 67
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Chapter 3: Memory
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Implementation
•Data Flip Flop
•Registers
•RAM
•Project 3: Chips
•Project 3: Guidelines
Chapter 3: Memory
Abstraction
•Representing time
•Clock
•Registers
•RAM
•Counter
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 68
Guidelines
•Implement the chips in the order in which they appear in the project guidelines
•If you don’t implement some chips, you can still use their built-in implementations
•No need for “helper chips”: Implement / use only the chips we specified
•In each chip definition, strive to use as few chip-parts as possible
•You will have to use chips implemented in previous projects;
•For efficiency and consistency’s sake, use their built-in versions, rather than your
own HDLimplementations.
That’s It!
Go Do Project 3!
For technical reasons, the chips of project 3 are organized in two sub-folders
named projects/03/a and projects/03/b
When writing and simulating the .hdl files, keep this folder structure as is.
Guidelines
•Implement the chips in the order in which they appear in the project guidelines
•If you don’t implement some chips, you can still use their built-in implementations
•No need for “helper chips”: Implement / use only the chips we specified
•In each chip definition, strive to use as few chip-parts as possible
•You will have to use chips implemented in previous projects;
•For efficiency and consistency’s sake, use their built-in versions, rather than your
own HDLimplementations.
That’s It!
Go Do Project 3!
For technical reasons, the chips of project 3 are organized in two sub-folders
named projects/03/a and projects/03/b
When writing and simulating the .hdl files, keep this folder structure as is.
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 69
Nand to Tetris Roadmap: Hardware
assembler
Nand
hardware platformabstraction
computerabstraction
ALU, RAMabstraction
elementary
logic gates
building a
computerbuilding
chipsbuilding
gates
p3
p5p4
abstraction
machine
language
p6
p2
p1
This lecture / project:
Build the computer’s RAM
Nand to Tetris Roadmap: Hardware
assembler
Nand
hardware platformabstraction
computerabstraction
ALU, RAMabstraction
elementary
logic gates
building a
computerbuilding
chipsbuilding
gates
p3
p5p4
abstraction
machine
language
p6
p2
p1
This lecture / project:
Build the computer’s RAM
Nand to Tetris / www.nand2tetris.org / Chapter 3 / Copyright © Noam Nisan and Shimon Schocken Slide 70
Nand to Tetris Roadmap: Hardware
assembler
Nand
hardware platformabstraction
computerabstraction
ALU, RAMabstraction
elementary
logic gates
building a
computerbuilding
chipsbuilding
gates
p3
p5p4
abstraction
machine
language
p6
p2
p1
Next two lectures / projects:
We’ll build the computer (p5)
But first, we’ll get acquainted with the computer’s machine language (p4).
Nand to Tetris Roadmap: Hardware
assembler
Nand
hardware platformabstraction
computerabstraction
ALU, RAMabstraction
elementary
logic gates
building a
computerbuilding
chipsbuilding
gates
p3
p5p4
abstraction
machine
language
p6
p2
p1
Next two lectures / projects:
We’ll build the computer (p5)
But first, we’ll get acquainted with the computer’s machine language (p4).
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