MICROCONTROLLER 8051 ARCHITECTURE BASIC.ppt

BASIC ARCHITECTURE OF MICROCONTROLLER 8051

1. MICROCONTROLLER LAB -8051
Balaji Ramakrishna

2. MICROCONTROLLERS
Prof. Cherrice Traver
ECE/CS
-
352: Embedded Microcontroller
Systems
CPU
ROM
RAM
I/O
A single chip
Subsystems:
Timers, Counters, Analog
Interfaces, I/O interfaces
Memory

3. PINDIAGRAM

4. COMMONMICROCONTROLLERS
•Atmel
•ARM
•Intel
•8-bit
•8XC42
•MCS48
•MCS51
•8xC251
•16-bit
•MCS96
•MXS296
•National Semiconductor
•COP8
•Microchip
•12-bit instruction PIC
•14-bit instruction PIC
•PIC16F84
•16-bit instruction PIC
•NEC
•Motorola
•8-bit
•68HC05
•68HC08
•68HC11
•16-bit
•68HC12
•68HC16
•32-bit
•683xx
•Texas Instruments
•TMS370
•MSP430
•Zilog
•Z8
•Z86E02

5. THENECESSARYTOOLSFORA
MICROPROCESSOR /CONTROLLER
CPU: Central Processing Unit
I/O: Input /Output
Bus: Address bus & Data bus
Memory: RAM & ROM
Timer
Interrupt
Serial Port
Parallel Port

6. MICROCONTROLLER ARCHITECTURES
CPU
Program
+ Data
Address Bus
Data Bus
Memory
Von Neumann
Architecture
CPU
Program
Address Bus
Data Bus
Harvard
Architecture
Memory
Data
Address Bus
Fetch Bus
0
0
0
2
n

7. “ORIGINAL” 8051 MICROCONTROLLER
Oscillator
and timing
4096 Bytes
Program
Memory
128 Bytes
Data
Memory
Two 16 Bit
Timer/Event
Counters
8051
CPU
64 K Byte
Bus
Expansion
Control
Programmable
I/O
Programmable
Serial Port Full
Duplex UART
Synchronous
Shifter
Internal data bus
External interrupts
subsystem interrupts
Control
Parallel ports
Address Data Bus
I/O pins
Serial Input
Serial Output

8. 8051 ARCHITECTURE

9. RAM memory space allocation in the 8051
7FH
30H
2FH
20H
1FH
17H
10H
0FH
07H
08H
18H
00H
Register Bank 0
(Stack) Register Bank 1
Register Bank 2
Register Bank 3
Bit-Addressable RAM
Scratch pad RAM

10. Memory space

11. BITADDRESSABLERAM
Figure 2-6
Summary
of the 8051
on-chip
data
memory
(RAM)

12. BITADDRESSABLERAM

13. PROGRAMSTATUSWORD(PSW)

14. ACCESSINGEXTERNAL
DATAMEMORY

15. ACCESSINGEXTERNAL
CODEMEMORY

16. INTERFACINGWITHEXTERNALROM

17. EXTERNALMEMORY

18. EXTERNALMEMORYTIMINGDIAGRAM

19. THEEA' (EXTERNALACCESS) PINISUSEDTOCONTROLTHEINTERNAL
OREXTERNALMEMORYACCESS.
THESIGNAL0 ISFOREXTERNALMEMORYACCESSANDSIGNAL1 FOR
INTERNALMEMORYACCESS.
THEPSEN' (PROGRAMSTOREENABLE) ISFORREADINGEXTERNAL
CODEMEMORYWHENITISLOW(0) ANDEA ISALSO0.
THEALE (ADDRESSLATCHENABLE) ACTIVATESTHEPORT0 JOINED
WITHPORT2 TOPROVIDE16 BITEXTERNALADDRESSBUSTOACCESS
THEEXTERNALMEMORY. THEALE MULTIPLEXESTHEP0:
ALE=1 FORLATCHINGADDRESSONP0 ASA0-A7 INTHE16 BIT
ADDRESSBUSS, ALE=0 FORLATCHINGP0 ASDATAI/O.
P0.XISNAMEDADXBECAUSEP0 ISMULTIPLEXEDFORADDRESSBUS
ANDDATABUSATDIFFERENTCLOCKTIME.
WR' PROVIDESTHESIGNALTOWRITEEXTERNALDATAMEMORY
RD' PROVIDESTHESIGNALTOREADEXTERNALDATAANDCODE
MEMORY.

20. ACCESSINGROM USINGINDEXED
ADDRESSING

21. INDEXEDADDRESSING

22. PORT0

23. PORT1

24. PORT2

25. PORT3

26. Thereare48-bitports:P0,P1,P2andP3.Allofthemaredual
purposeportsexceptP1whichisonlyusedforI/O.Thefollowing
diagramshowsasinglebitinan8051I/Oport.
Whenaprogramwritesaonebytevaluetoaportorasinglebitvalue
toabitofaport,assigningthevaluetotheportasfollows:
P1=0x12;orP1^2=1;
P1representsthe8bitsofport1andP1^2isthepin#2oftheport1
of8051definedinthereg51.hofC51,aCdedicatedfor8051
family.
Whendataiswrittentotheportpin,itfirstappearsonthelatchinput
(D)andisthenpassedthroughtotheoutput(Q)andthroughan
invertertotheFieldEffectTransistor(FET).
Ifyouwritealogic0totheportpin(DFFQ=0),itisinvertedtologic1
andturnsontheFETgate.Itmakestheportpinconnectedto
ground(logic0).
Iflogic1iswrittentotheportpin(DFFQ=1),,thenitisinvertedtoa
logic0andturnsofftheFETgate.Thereforethepinisatlogic1
becauseitisconnectedtohigh.

27. PORT P1 (Pins 1 to 8): The port P1 is a port dedicated for general
I/O purpose. The other ports P0, P2 and P3 have dual roles in
addition to their basic I/O function.
PORT P0 (pins 32 to 39):When the external memory access is
required then Port P0 is multiplexed for address bus and data bus
that can be used to access external memory in conjunction with
port P2. P0 acts as A0-A7 in address bus and D0-D7 for port data.
It can be used for general purpose I/O if no external memory
presents.
PORT P2 (pins 21 to 28): Similar to P0, the port P2 can also play a
role (A8-A15) in the address bus in conjunction with PORT P0 to
access external memory.

28. PORT P3 (Pins 10 to 17):
In addition to acting as a normal I/O port,
P3.0 can be used for serial receive input pin(RXD)
P3.1 can be used for serial transmit output pin(TXD)
in a serial port,
P3.2 and P3.3 can be used as external interrupt
pins(INT0’ and INT1’),
P3.4 and P3.5 are used for external counter input
pins(T0 and T1),
P3.6 and P3.7 can be used as external data memory
write and read control signal pins(WR’ and RD’)read
and write pins for memory access.