microelectronics-6ed-ch8-ppt-2025-spring

電子學2上課的ppt

1. Microelectronic Circuits II
Differential and Multistage Amplifiers
Chia-Ming Tsai
NYCU
Department of Electrical Engineering

2. Outlines
•MOS Differential Pair
•BJT Differential Pair
•Common-Mode Rejection
•DC Offset
•Differential Amplifier With A Current-Mirror Load
•Multistage Amplifiers

3. What To Learn
•The essence of the operation of the MOS / BJT differential
amplifiers :
–Amplify differential signals
–Reject common-mode noise or interference
•The analysis and design of MOS and BJT differential amplifiers.
•Differential-amplifier circuits of varying complexity, using passive
resistive loads, current-source loads, and cascodes.
•Multi-stage amplifiers composed of two or more stages in
cascade.
–Two-stage CMOS op amp
–Four-stage bipolar op amp

4. Introduction
•The differential-pairor differential-amplifier configuration is the
most widely used building block in analog integrated-circuit
design.
–For instance, the input stage of every op ampis a differential
amplifier.
–Also, the BJTdifferential amplifier is the basis of a very-high-
speed logic-circuit family, called emitter-coupled logic (ECL).
•Initially invented in the 1940sfor use with vacuum tubes, the
basic differential-amplifier configuration was subsequently
implemented with discrete bipolar transistors.
•However, it was the advent of integrated circuits (ICs) that has
made the differential pair extremely popular in both bipolar and
MOS technologies.

5. Single-Ended Amplifiers
•Pros : simple, low-power, low-cost …
•Cons : very sensitive to supply noise and environmental noise

6. Differential Amplifiers
•Advantage : better immunity to supply noise and environmental
noise

7. Single-Ended vs. Differential Signaling
•A single-ended signalis defined as one that is measured with respect to a
fixed potential.
•A differential signal is defined as one that is measured between two nodes.
•Common-mode level : thecenterpotential in difference signaling.
Single-ended signal Differential signal

8. Single-Ended vs. Differential Signaling
•Reduction of coupled noise by using differential operation (clock noise
cancellation)
•Differential signaling : increase the maximum achievable voltage swings.
The peak to peak swing is equal to twice that of a single-ended signal.
–Example :
•Single-ended :
•Differential :tV
o sin1 tVVtVtV
oooo  sin2 sin1 sin1 


9. Bipolar vs. CMOS Technology

10. The MOS Differential Pair
2
, voltage)mode-(common
2121
I
iiVVVVvv
DDGSCMSCMGG

•Assume Q
1and Q
2are perfectly-matched and operated in saturation region.
•An ideal current source with R
out=is assumed. 
LWk
I
VV
L
W
kVV
L
W
k
I
VVV
n
OVOVntGSntGSOV
/
,
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1
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1
2
, voltageoverdriveLet
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Common-modeoperation

11. V
CM= 0 V V
CM= 1 V
V
CM= -0.2 V

12. Input Common-Mode Range
•It’s the range of V
CM over which
the differential pair operates
properly.
•Thehighest V
CMis limited by the
requirement that Q
1and Q
2
remain in saturation.
•The lowest V
CMis determined by
the need for a sufficient voltage
V
CSacross current source Ifor it
to operate properly. tDDDtDCM
DDDDDD
VR
I
VVVV
R
I
VVVV


2

2
max
21 OVtCSSSGSCSSSCM
CSSSGSCM
VVVVVVVV
VVVV


min
)(

13. •If v
idis increased beyond v
idmax, i
D1
remains equal toI.
•The range of differential-mode operation:
the current I can be steered from one
transistor to the other by varying v
idin the
range :
Operation with a Differential Input Voltage21

GSGSid
vvv   

OVtOVtSGSid
OVtntGS
tGS
'
nD
tS
VVVVvvv
VVLWkIVv
I Vv
L
W
ki
Vv
22
2//2

2
1
off)cut (Q
1max
'
1
2
11
2




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



 OVtGS
VVV 2
1
 OVidOV
VvV 22 
•Differential input voltage :
•If the current Iis fully switched to Q
1and
Q
2is cutoff. (@A)
Bias point
A

14. Large-Signal Operation 
 
2
2
'
2
2
1
'
1
2
1
2
1
(I)
tGSnD
tGSnD
Vv
L
W
ki
Vv
L
W
ki

  
 
tGSnD
tGSnD
Vv
L
W
ki
Vv
L
W
ki


2
'
2
1
'
1
2
1
2
1
(II) (1) ...
2
1

(III)
'
21
2121
idnDD
idGGGSGS
v
L
W
kii
vvvvv

  
 
L
W
kI
vv
I
L
W
k
I
i
L
W
kI
vv
I
L
W
k
I
i
n
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n
idid
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'
2
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2
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2
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1
/
2/
1
22
/
2/
1
22
(V)

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 12
2'
21
21
2
1
2
(2) ...
(IV)
DD
idnDD
DD
iIi
v
L
W
kIii
Iii




15. Comparison of Linear Rangem
id
OV
id
Dm
id
OV
id
DOV
id
g
vI
V
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ig
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v
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2222
,
2222

2
If
21 OVOV
D
mDDid
V
I
V
i
g
I
iiv 
1
21
2
,
2
0 As
•At the bias (quiescent) point :
•For small-signal operation (linear region) :
•The linearity can be increased by increasing the overdrive voltageV
OV
(use smaller W/L), but at the expense of reducing g
m(gain). 2
2
2
1
2'
2/
1
22

2/
1
22
point) bias(at
2
1
2



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OV
id
OV
id
D
OV
id
OV
id
D
OVn
V
v
V
IvI
i
V
v
V
IvI
i
V
L
W
k
I
Bias point

16. Small-Signal Operation : Differential Gain
•The common-mode voltage : V
CM
–It is needed to set the dc voltage of the MOSFET gates.
–Typically V
CMis at the middle value of the power supply.
•The differential input signal : v
id
•This would be thecase, for instance, if the differential amplifier were fed from the
output of anotherdifferential-amplifier stage.

17. Differential Gain
•From the symmetry of the circuit and the balanced manner in which v
idis applied, the
signal voltage at the joint source connection must be zero, acting as asort of virtual
ground.
•Assume v
id/2<<V
OV(The small-signal approximation can be applied.)
•One advantage of taking the output differentially is an increase in gain by a factor of 2
(6dB).
Differential gain :
For r
o = .Virtual
ground

18. Differential Gain
An alternative view of the small-signal differential
operation of the differential pair
Differential half circuit

19. Effect of the MOSFET’s r
o
•By the virtual ground assumption, using the differential half circuit
•The differential gain is the same as that of a single-stage CS amplifier.      vrRgvvv
v
rRgv
v
rRgv
idoDmooo
id
oDmo
id
oDmo
||
2
||
2
||
1221
 oDDeff rRR ||

20. Example 8.2

21. BJT Differential Pair
Input Data = 1 Input Data = 0

22. Input Common-Mode Range
•The upper end of V
CMis determined
by Q
1and Q
2leaving the active
mode and entering saturation.
Thus,
•The lower end of the V
CMrange is
determined by the need to provide a
certain minimum voltage V
CSacross
the current source I to ensure its
proper operation. Thus,

23. Basic Operation

24. Transfer characteristics of the BJT differential pair assuming α 1.
•The linear region of the emitter coupled pair is less than 4V
T, which is much smaller
than that for the MOS pair, .OV
V2

25. Improved Linearity by Emitter Degeneration
•The linear range of the emitter coupled pair can be extended by using
degeneration resistor R
e, but at the expense of smaller gain (g
meff).
This technique can also be applied to MOS differential pair.

26. Small-Signal Operation

27. An Alternative Viewpoint

28. •Assume the current source is ideal, (output resistance is infinite)
•Input differential resistanceem
m
meff
id
meff
ee
id
c
ee
id
ee
id
m
e
id
ec
e
id
e
T
E
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ee
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v
i
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v
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r
v
i
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V
I
V
rR


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
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
1222

22
: With
22

2

2/
: Without


 eee
b
id
ide
id
m
e
id
ece
b
id
id
eide
be
RrRr
i
v
RR
v
g
r
v
iirr
i
v
R
rvi
iR
1)(22)21)(2( : With
22
21)2(
1
2/
1
: Without












An Alternative Viewpoint

29. The Differential Half-Circuit
•The differential signal
v
idis applied in a
complementary (push-
pull or balanced)
manner.
•From symmetry, it
follows that the signal
voltage at the emitters
will be zero (virtual
ground).
•Note that the finite
output resistance R
EE
of the current source
will have no effect on
the operation.
Differential half-circuit

30. Example 8.3

31. Differential Amp. with Current Source Load
•To obtain higher gain, the passive resistances (R
D) can be replaced with
current sources. )||(
311 oomd
rrgA

32. Cascode Configuration2
id
m
v
g 2
id
Cm
v
Rg oR 2
id
m
v
g 2
id
v

33. Cascode Differential Amplifier
•Gain can be increased via cascode configuration.1
3 3 1
5 5 7
( )
( )
( )
od
d m on op
id
on m o o
op m o o
v
A g R R
v
R g r r
R g r r




34.  
 
cmd
d
cmd
d
dd
cmd
dd
cmcm
iddicmcmd
id
A
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
 Common-Mode Rejection Ratio (CMRR)

35. Common-Mode Rejection Ratio (CMRR)
R
g
R
v
v
v
v
SS
m
D
icm
o
icm
o
2
1
21


R
R
v
v
v
v
SS
D
icm
o
icm
o
2
21

•Let V
icmrepresents a disturbance
of interference signal that is
coupled to both input terminals.
•CM half circuit:
•Usually,
•If the output of the differential pair is taken single-endedly:
•If the output of the differential pair is taken differentially:(poor)
2
1
||
2
||
,
,
,, SSm
SEcm
SEd
SEDmSEd
SS
D
SEcm
Rg
A
A
CMRRRgA
R
R
A  (perfect) || 0
1212
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d
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oo
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A
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v
vv
A
v
vv
A mSS
gR 1
CM half circuit

36. Effect of R
DMismatch on CMRR 
DD
SSm
cmd
d
Dmd
SS
D
icm
oo
cmd
icm
SS
D
oo
icm
SS
DD
o
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o
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,
2
2

2
2

2
, 1 If

12
12
2
1
21
21
2121
R
D R
D+R
D
g
m g
m
Neglect r
oeffect

37. Effect of g
mMismatch on CMRR 
 
mm
SSm
cmd
d
Dmd
SSm
Dm
cmd
icm
SSm
Dm
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m
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38. Example 8.4   
  (Good) m89.0
5
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V 47.4 k 36.22 M 1m2
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39. CMRR for The BJT Case
Rr
R
v
v
v
v
EEe
C
icm
o
icm
o
2
21



R
R
v
v
v
v
EE
C
icm
o
icm
o
2
21

•Let v
icmrepresents a disturbance of
interference signal that is coupled
to both input terminals.
•CM half circuit:
•Usually,
•If the output of the differential pair is taken single-endedly
•If the output of the differential pair is taken differentiallyEEm
SEcm
SEd
SECmSEd
SS
C
SEcm
Rg
A
A
CMRRRgA
R
R
A 
,
,
,,

2
1
||
2
|| 
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
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cmd
d
Cm
id
oo
d
icm
oo
cmd
A
A
CMRRRg
v
vv
A
v
vv
A || 0
1212
CM half-circuit rR
eEE and 1

40. CMRR for The BJT Case
•Any mismatch between the two sides of the differential amplifier will result in v
od
acquiring a component proportional to v
icm.
•For example, a mismatch R
Cbetween the two collector resistances results in
•Since α 1, r
e<< 2R
EE, it can be approximated and written in the form
•The common-mode rejection ratio can now be found as
•Thus, to obtain a high CMRR, we design the current source to have a large output
resistance R
EEand strive for close matching of the collector resistances.Cmd RgA

41. Input Common-Mode Range

42. Common-Mode Input Resistance

43. Example 8.5

44. Input Offset Voltage of the MOS Differential Pair
•Consider the basic MOS differential amplifier with both inputs grounded,
practical circuits exhibit mismatches that result in a DC output voltage V
o.
•Output offset voltage : V
o(@ V
i1 = V
i2)
•Input offset voltage : V
OS= V
o/A
d(V
odivided by the differential gain of the
amplifier A
d )
•If we apply a voltage (–V
OS)between the inputterminals of the differential
amplifier, then the output voltage will be reduced to zero.

45. Input Offset Voltage of MOS Differential Pair
•Three factors contribute to the input offset voltage of the
MOS differential pair
–Mismatch in load resistances R
D
–Mismatch in (W/L) ratios (or transconductance parameters k
n,p)
–Mismatch in threshold voltages V
t

46. Input Offset Voltage (1)
•Consider mismatch in load resistance R
D
•Consider a differential pair in which the two transistors are operating at
V
OV= 0.2 V, and each drain resistance is accurate to within 1%. We have








































 






 













D
OV
Dm
D
V
o
OSDDDo
OVOV
m
D
DDDD
D
DDDD
D
DD
D
DD
R
RV
Rg
R
I
A
V
VR
I
VVV
V
I
V
I
g
R
R
I
VV
R
R
I
VV
R
RR
R
RR
2

2

2

2

22
22

2
2
112
D
2
1
2
1 mVV
R
R
OS
D
D
202.01.0 02.0
1 


47. •Consider the effect of a mismatch in (W/L) ratios:
)/(
)/(
2/


)/(
)/(
2

2


)/(2
)/(
22
)/(2
)/(
22

2
1
2
1
2
21
D
2
1
2
1
LW
LWV
VI
I
g
I
V
LW
LWI
III
V
I
V
I
g
LW
LWII
I
LW
LWII
I
L
W
L
W
L
W
L
W
L
W
L
W
OV
OVm
OS
OVOV
m


































































Input Offset Voltage (2)

48. •Consider the effect of a mismatch V
tin threshold voltages : 
 
 
 
 
 
t
m
OS
tmt
tGStGS
t
tGSn
tGS
t
tGSn
t
tGSn
tGS
t
tGSn
tGS
t
tGSn
t
tGSn
t
tt
t
tt
tGSt
V
g
I
V
VgV
VV
I
VV
V
VV
L
W
kIII
VV
V
VV
L
W
k
V
VV
L
W
kI
VV
V
VV
L
W
k
VV
V
VV
L
W
k
V
VV
L
W
kI
V
VV
V
VV
VVV




































 

























 













3
2'
21
2'
2
'
2
2'
2
2'
2
'
1
2
1


2
2
2
2
1

1
2
1

22
1
1
2
1

2
1
2
1

22
1

2
2
Let . 2 Assume
Input Offset Voltage (3)

49. •The total input offset voltage can be derived as
Total Input Offset Voltage
2
22
2
3
2
2
2
1
/
)/(
22

t
OV
D
DOV
OSOSOSos
V
LW
LWV
R
RV
VVVV


















50. V
OSfor The BJT CaseOS
V   o
V   1B 2B

51. V
OSDue to R
CMismatch

52. V
OSDue to I
SMismatch

53. Total V
OS

54. Input Offset Currents for BJT Case
•Input bias current
•Input offset current

55. Differential Amplifier with a Current-Mirror Load
•Taking the output differentially hasthree major advantages:
1.It decreases the common-mode gain and thus increases the CMRR.
2.It decreases the input offset voltage.
3.It increases the differential gain by a factor of 2 (6 dB).
•At least the first stage in an IC amplifier such as an op amp is
differential-in, differential-out.
•Nevertheless, it is usually required at some point to convert the
signal from differential to single-ended; for instance, to connect it to
an off-chip load.

56. Differential-to-Single-Ended Conversion
•Note that the current signal in Q
1is not utilized, and as a result, the
gain achieved is 6 dB lower than the differential-output case.
Small-signal modelDm
id
o
V
Rg
v
v
A
2
1


57. Current-Mirror-Loaded MOS Differential Paircurrent)output (zero 0

:grounded inputs When
3



O
SGDDAO
I
VVVV
I
O = 0
A

58. Current-Mirror-Loaded MOS Differential Pair
•For small-signal common-mode
input signals, i
D4cancels i
D2.
•For small-signal differential input
signals, i
D4matches i
D2.0
s
v icmsvv (Good) 0
0 & 0


cm
OO
A
vi (Good)gain aldifferenti Double
2

ii
O

59. Differential Gain
Output equivalent circuit
for differential input
signals.
G
md: Differential short-
circuit transconductance
R
o: Output resistance
•It can be shown that
R
od= output resistance of differential amp
R
om= output resistance of current mirror
•The open-circuit differential voltage gain
can be found as
•Let g
m1,2 =g
mand r
o2,4= r
o.
where A
0is the intrinsic gain.omodooo
oommd
RRrrR
rgG
||||
)(neglect
42
3,12,1

  
omodmomd
id
o
d RRgRG
v
v
A ||
2,1 0
2
1
2
1
ArgA
omd


60. Derivation of G
md3
1
1
m
o
g
R 0
2

o
R 0
0
2
1


d
d
v
v 





43
2,1
for
mm
mm
idmo
gg
gg
vgi

61. Derivation of R
o





1
for 2
22
21
22
om
mm
oo
rg
gg
rR LR 402
||
o
x
rr
v


62. BJT Differential Pair with a Current-Mirror
Loadooo
rrr 
42

63. Differential Gain: BJT vs. MOS
•Pros:
–The gain is much larger because g
mr
ofor the BJT is more than an order
of magnitude greater than g
mr
oof a MOSFET.
•Cons:
–Low differential input resistance for BJT amplifiers:
–For multistage amplifiers, the overall voltage gain will be drastically
reduced by the low R
idof the subsequent BJT stage.2id
R 3id
R

64. Systematic Input Offset Voltage
•This circuit suffers from a systematic offset voltage due to theerror in the
current transfer ratio of the current-mirror load caused by the finite of Q
3,4.

finite todue imbalance Bias
2
1
21









 II 1I 2I 2I 2
2
I


65. Common-Mode Gain and CMRR
G
mcmis the common-mode
short-circuit transconductanceomcmcm RGA 42
||
ooo
rrR

66. Derivation of G
mcm
a b) ,(for
2,12,1 ooommm rrgg 
KCL @ a,b,S
KCL @ D
2

67. Derivation of G
mcm
•Since g
mr
o>> 1, g
mR
SS>> 1, and R
im<< r
o.
•Two separate reasons for the nonzero G
mcm
–A
m1
–R
im0 ( It leads to i
1i
2.)





0
1
if 0 :
im
m
mcm
R
A
G

68. Derivation of G
mcm
•For the simple MOS mirror, we have
•The common-mode gain can be found as
•|A
cm| is small and can be reduced by using a current source with a large R
SS.)||(
1
2
11
2
2
11
2
1

)1(
2
)1(
2
1

1
1
1
1/1
1
||
1
.1 and 1 Assume
3333333
3333
3
3
3
33
oomSSomomomSS
m
o
im
m
SS
mcm
omom
m
m
o
m
im
om
rrgRrgrgrgR
A
r
R
A
R
G
rgrg
A
g
r
g
R
rgε






































 SSm
cm
oo
oo
oom
oo
SS
omcmcm
Rg
A
rr
rr
rrg
rr
R
RGA
343
2
33
42
2
1
For
)||(
||
2
1






 imR i
i o
i i
o
m
i
i
A

69. CMRR
•The CMRR will be large and it can be increased by raising the R
SS.  
  
normally) n larger tha(Much
||2 For
||2

)||(2
1 have weNow
32,1
4,3
2,1
332,1
2,1
33
2,1
SE
omodm
CMRR
SSm
omo
odoo
oomSSm
mcm
m
cm
d
oom
o
SS
omcmcm
omd
CMRR
RRgRgCMRR
Rr
Rrr
rrgRg
G
g
A
A
CMRR
rrg
R
R
RGA
RgA
SE
















70. Multistage Amplifiers
•To illustrate the circuit structure and the method of
analysis of multistage amplifiers, we will present two
examples:
1.Atwo-stage CMOS op amp
2.Afour-stage bipolar op amp

71. A Two-Stage CMOS Op Amp
•The circuit utilizes two power supplies,
which can range from ±0.9 V for the
0.18-μm technology down to ±0.5 V for
the 65-nm technology.
•The current mirror formed by Q
8and
Q
5supplies the differential pair Q
1−Q
2
with bias current. The W/L ratio of Q
5
is selected to yield the desired bias
current I.
•The input differential pair is loaded
with the current mirror Q
3,4.
•The second stage consists of Q
6,
which is a CS amplifier with a current-
source load Q
7.
•A capacitor C
Cis included in the
negative-feedback path of the second
stagefor improving the stability. (By
using the Miller effect)
•Voltage gain of the first stage :
•Voltagegain of the second stage :
•DC open-loop gain of the op amp : A
1A
2
Stage-1Stage-2

72. A Two-Stage CMOS Op Amp
•The op ampis not suitable for driving low-impedance loads due to its high
R
out= (r
o6||r
o7).
•This circuit is very popular and is used frequently in VLSI circuits, where the
op amp needs to drive only a small capacitive load, for example, in
switched-capacitor circuits.
•Also, when this op amp is utilized, negative feedback is applied, which
results in reducing R
out.
•The simplicity of the circuit results in an op amp of reasonably good quality
realized in a very small chip area.

73. Input Offset Voltage
•The device mismatches inevitably present in the input stage give rise to an
input offset voltage. Because device mismatches are random, the resulting
offset voltage is referred to as random offset.
•Another type of input offset voltage that can be present even if all
appropriate devices are perfectly matched is the systematic offset. It can be
minimized by careful design.
•Compared to the BJT op amps, the input offset problem is usually much
more pronounced in CMOS op amps because their gain-per-stage is rather
low.

74. Zero Systematic Offset
•The condition for achieving zero systematic offset is I
6= I
7 .346 GSGSGS VVV  6
I 7
I 2I 2I

75. A Bipolar Op Amp
•The bipolar op amp consists of
four stages.
•The 2
nd
stage performs the
differential to single-ended
conversion, which results in a
loss of gain by a factor of 2.
•The 3
rd
stage provides some
voltage gainand the essential
function of dc level shifting.
•The output stage consists of
emitter follower.
Input
stage
2
nd
stage
3
rd
stage
Output
stage

76. Analysis Using Current Gains
Each factor is either thecurrent gain ofa
transistor or theratio of a current divider.
(differential)
(differential)21,1 RRR
diffo 