microprocessor systems Lecture 2 Parallel port

microprocessor systems Lecture 2 Parallel port

1. Parallel Port Programming

2. Components Microprocessor SRAM Flash Memory Input ports Output ports Parallel Serial Sensor Motor Siren DAC ADC Rom RISC Microprocessor

3. Why? Some devices are parallel by nature Easier to program Error handling

4. PRINTER & INTERFACING IN THE PC steps in computer & printer communication BUSY DATA ACK STROBE

5. PRINTER & INTERFACING IN THE PC data lines and grounds Input pins DATA 1 to DATA 8 provide a parallel pathway for 8-bit data sent by the PC to the printer. Fig. 18-8 DB25 Printer Pin These are all output pins from the printer to the PC used by the printer to indicate its own status.

6. MOV DX,378H OUT DX,00011101b

7. PRINTER & INTERFACING IN THE PC Centronics printer interface pins The Centronics type parallel printer interface is the printer interface standard in the x86 PC. Referred to as Epson FX 100 standard, it is a 36-pin interface connector with pins labeled as 1 to 36. Many are used for ground, to reduce electrical noise. The 36 Centronics pins can be grouped as follows. 1. The data lines carry data, sent by the PC to the printer. 2. The printer status signals indicate the printer status at any given time. 3. Printer control signals tell the printer what to do. 4. Ground signals provide an individual ground return line for each data line, and certain control & status lines.

8. PRINTER & INTERFACING IN THE PC data lines and grounds BUSY (pin 11) - is high if the printer is not ready to accept a new character. This pin is high when the printer is off line or when it is printing & can’t accept any data. As long as this pin is high, the PC will not transfer data to the printer. PE (pin 12) - used by the printer to indicate it is out of paper.

9. PRINTER & INTERFACING IN THE PC data lines and grounds ERROR (pin 15) - normally high output, activated ( goes low ) in conditions such as out of paper, off line state, or jammed printhead, in which the printer cannot print. SLCT (pin 13) is active-high , from printer to PC when the printer is on & online. ACKNLG (pin 10) - used to acknowledge printer receipt of data & that it can accept a new character.

10. PRINTER & INTERFACING IN THE PC printer control signals STROBE (pin 1) and ACKNLG are the most widely used signals among control and status pins. When the PC presents a character to the data pins of the printer, it activates the STROBE pin of the printer. Telling it that there is a byte sitting at the data pins. INIT (pin 16) - an input to the printer, normally high . When it is activated ( active-low ) it resets the printer.

11. PRINTER & INTERFACING IN THE PC printer control signals AUTO FEED XT & SLCT IN are two other control signals in the printer.

12. PRINTER & INTERFACING IN THE PC steps in computer & printer communication The computer checks to see if a BUSY signal from the printer indicates the printer is ready (not busy). The computer puts 8-bit data on the data line connected to the printer data pins. The computer activates STROBE by making it low . Prior to asserting the printer input STROBE pin, the data must be at the printer's data pins at least for 0.5 µs. The STROBE must stay low for at least 0.5 µs before the computer brings it back to high . The data must stay at the printer's data pins at least 0.5 µs after the STROBE pin is deasserted (brought high ).

13. PRINTER & INTERFACING IN THE PC steps in computer & printer communication The activation of STROBE causes the printer to assert its BUSY output pin high character. Indicating to the computer to wait until it finishes taking care of the last byte.

14. PRINTER & INTERFACING IN THE PC steps in computer & printer communication When the printer is ready to accept another byte, it sends the ACKNLG signal back to the computer by making it low. The printer keeps the ACKNLG signal low only for 5 µs. At the rising edge of ACKNLG, the printer makes the BUSY (not BUSY = ready) pin low to indicate that it is ready to accept the next byte. The CPU can use either the ACKNLDG or BUSY signals from the printer to initiate the process of sending another byte to printer. Some systems use BUSY and some use ACKNLG.

15. Components Microprocessor SRAM Flash Memory Input ports Output ports Parallel Serial Sensor Motor Siren DAC ADC Rom RISC Microprocessor

16. 8255 I/O PROGRAMMING

17. 8088 INPUT/OUTPUT INSTRUCTIONS All x86 processors, 8088 to Pentium ® , can access external devices called ports using I/O instructions. Memory can contain both opcodes and data. I/O ports contain data only Two instructions: “ OUT ” and “ IN ” send data from the accumulator ( AL or AX ) to ports or bring data from ports into the accumulator.

18. 8088 INPUT/OUTPUT INSTRUCTIONS 8-bit data ports 8088 I/O operation is applicable to all x86 CPUs. The 8-bit port uses the D0–D7 data bus for I/O devices. Register AL is used as the source/destination for IN/OUT instructions. To input or output data from any other registers, the data must first be moved to the AL register. Instructions OUT and IN have the following formats:

19. 8088 INPUT/OUTPUT INSTRUCTIONS how to use I/O instructions I/O instructions are used in programming 8- and 16-bit peripheral devices. Printers, hard disks, and keyboards. For an 8-bit port, use immediate addressing : For more ports, use 16-bit port address instruction.

20. 8088 INPUT/OUTPUT INSTRUCTIONS how to use I/O instructions 16-bit port address instruction using register indirect addressing mode with register DX . This program toggles port address 300H continuously. Only DX can be used for 16-bit I/O addresses. Use register AL for 8-bit data.

21. I/O ADDRESS DECODING AND DESIGN

22. I/O ADDRESS DECODING AND DESIGN The concept of address bus decoding for I/O instructions is exactly the same as for memory. 1. The control signals IOR and IOW are used along with the decoder. 2. For an 8-bit port address, A0 – A7 is decoded. 3. If the port address is 16-bit (using DX ), A0 – A15 is decoded.

23. Why? Suppose you want to read temperature with a microcontroller

24. Why? Now also we want to detect light density

25. Why? We can connect both of them

26. Why? We need to add extra controlling part to Connect/disconnect sensors

27. Why? But how to decide?

28. Why? We could use extra enable/disable pin

29. Why? Final touch

30. Why? We call them Input port 1 Input port 0 Data Bus Address Bus

31. Why? For extra devices we need more address lines Input port 3 Input port 2 What are these boxes?

32. Yes… it is a Tri-State buffer

33. What about Microprocessor?

34. We want to add an input device Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses

35. We can connect it directly Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses

36. But it will make a problem that it will overwrite anything on the system data bus Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses

37. We want to connect it only if its address on the address bus Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses

38. So we need to add a tristate buffer that activated upon the device address existence Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses

39. In addition, we need to ensure that it is an I/O address not a memory address Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses

40. So we connect IOR signal Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOR

41. But note: It is inverted Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOR

42. Address enable (AEN) should be taken into consideration. It means that the processor is using buses now. Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOR AEN

43. Microprocessor also needs a tristate buffers. It is like a manager but not the only user of system bus Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOR AEN

44. Microprocessor also needs a tristate buffers. It is like a manager but not the only user of system bus Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOR AEN

45. This is the 74LS244 chip Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOR AEN

46. But actually it takes inverted input. So we must add inverter Microprocessor INPUT Device … VCC VCC D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOR 1G 2G AEN

47. I/O ADDRESS DECODING AND DESIGN IN port design using 74LS244 Data from a data bus, must come in through a three-state buffer—referred to as tristated . Simple input ports we 74LS244 Octal Buffer Since 1G & 2G each control only 4 bits of 74LS244, they both must be activated for 8-bit input.

48. I/O ADDRESS DECODING AND DESIGN IN port design using 74LS244 74LS244 is widely used for buffering and providing high driving capability for unidirectional buses. The address decoder & the IOR control signal together activate the tri-state input.

49. I/O ADDRESS DECODING AND DESIGN IN port design using 74LS244 74LS244 as an entry port to the system data bus. Used for bidirectional buses Figure 11-6 Input Port Design for “IN AL,5H”

50. Now, what about output devices?

51. Of course we need tristate buffers to be able to disconnect the output device. Note: IOR is now IOW Microprocessor OUTPUT Device … D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOW LEDs AEN

52. However, it should be always ON. Output devices doesn’t change the line status. Microprocessor OUTPUT Device … D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOW LEDs VCC AEN

53. The main problem here is that the microprocessor is extremely faster that output devices Microprocessor OUTPUT Device … D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOW LEDs VCC AEN

54. And I do not want output device show any output unless it is selected Microprocessor OUTPUT Device … D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOW LEDs VCC AEN

55. Therefore, we need to add latches Microprocessor OUTPUT Device … D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOW LEDs VCC Q clk D Q clk D Q clk D AEN

56. Latches should activated using the address decoding circuit Microprocessor OUTPUT Device … D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOW LEDs VCC Q clk D Q clk D Q clk D AEN

57. This is the 74LS373 chip Microprocessor OUTPUT Device … D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOW LEDs VCC Q clk D Q clk D Q clk D OC G AEN

58. But approx. always ON signal consumes much power Microprocessor OUTPUT Device … D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOW LEDs VCC Q clk D Q clk D Q clk D OC G AEN

59. Lets make it inverted. So we should connect it to the ground instead of VCC Microprocessor OUTPUT Device … D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOW LEDs Q clk D Q clk D Q clk D OC AEN

60. Inversion of some signals happen due to power consumption saving or signal standards Microprocessor OUTPUT Device … D0 D1 D7 … D0 D1 D7 … A0 A1 A20 … … System Data Bus System Address Bus Local Buses IOW LEDs Q clk D Q clk D Q clk D OC AEN

61. I/O ADDRESS DECODING AND DESIGN using 74LS373 in an output port design 74LS373 can be used as a latching system for simple I/O ports. Pin OC must be grounded. 74LS373 D Latch

62. I/O ADDRESS DECODING AND DESIGN using 74LS373 in an output port design Design a decoding circuit for “OUT 99H, AL”. For an output latch, it is common to AND the output of the address decoder with control signal IOW . To provide the latching action.

63. I/O ADDRESS DECODING AND DESIGN using 74LS373 in an output port design

64. The question now. Do we need a decoding circuit for each single address?

65. Assume we have the address range 300H to 307H Each one of them needs a decoding circuit 300 H 301 H 302 H 307 H …

66. Instead of making a circuit for each address we can use 300 H 301 H 302 H 307 H … 300 H 301 H 302 H 303 H 304 H 305 H 306 H 307H Enable A0 A1 A2 AEN

67. This is 74LS138 chip 300 H 301 H 302 H 303 H 304 H 305 H 306 H 307H Enable A0 A1 A2 AEN G2 G1

68. I/O ADDRESS MAP OF x86 PCs 74LS138 as a decoder NANDs, inverters, and 74LS138 chips for decoders can be applied to I/O address decoding. 74S138 Decoder

69. 74LS138 showing I/O address decoding for an input port located at address 304H . Each Y output controls a single I/O device. Y4 output, together with the signal at IOR , controls Using 74LS138 for I/O Address Decoder Y0, with IOW can control a 74LS373 latch. I/O ADDRESS MAP OF x86 PCs 74LS138 as a decoder

70. I/O ADDRESS MAP OF x86 PCs 74LS138 as IBM PC I/O address decoder A0 to A4 go to individual peripheral input addresses. A5, A6, & A7 handle output selection of outputs Y0 to Y7. Pins A8, A9, & AEN all must be low to enable 74LS138. PC/XT Port Address Coding

71. I/O ADDRESS MAP OF x86 PCs

72. I/O ADDRESS MAP OF x86 PCs absolute vs. linear address decoding In decoding addresses, either all or a selected number of them are decoded. In absolute decoding, all address lines are decoded. If only selected address pins are decoded, it is called linear select decoding. Linear select is cheaper, but creates aliases, the same port with multiple addresses. If you see a large gap in the I/O address map of the x86 PC, it is due to the address aliases of the original PC.

73. I/O ADDRESS DECODING AND DESIGN memory-mapped I/O Communicating with I/O devices using IN and OUT instructions is referred to as peripheral I/O . Some designers also refer to it as isolated I/O or Port-mapped IO. This Method uses linear address decoding Intel VS. Motorola

74. I/O ADDRESS DECODING AND DESIGN memory-mapped I/O Some processors do not have IN & OUT instructions, but use Memory-mapped I/O . A memory location is assigned as an input or output port. Instructions access memory locations to access I/O ports. Instead of IN and OUT instructions. The entire 20-bit address, A0–A19 , must be decoded. The DS register must be loaded prior to accessing memory-mapped I/O. In memory-mapped I/O interfacing, control signals MEMR and MEMW are used. Memory I/O ports can number as high as 2 20 (1,048,576).

75. ADDRESS DECODING AND DESIGN memory-mapped I/O Some processors do not have IN & OUT instructions, but use Memory-mapped I/O . Memory-mapped I/O can perform arithmetic & logic operations on I/O data directly without first moving them into the accumulator. Memory-mapped I/O uses memory address space, which could lead to memory space fragmentation. Memory-mapped IO Port-mapped IO Same address bus to address memory and I/O devices Different address spaces for memory and I/O devices Access to the I/O devices using regular instructions Uses a special class of CPU instructions to access I/O devices Most widely used I/O method x86 Intel microprocessors - IN and OUT instructions

76. Examples of INPUT/OUTPUT Usage Decision making based on the data that was input.

77. port 61H and time delay generation Port 61H, a widely used port, can be used to generate a time delay. In any PC from the 286 to the Pentium ® . I/O port 61H has eight bits (D0–D7), of which D4 is of particular interest. In all 286 & higher PCs, D4 of port 61H changes its state, indefinitely every 15.085 microseconds (ms). Low for 15.085 ms. High for the same amount of time. Low again.

78. port 61H and time delay generation This program uses port 61H to generate a 1/2 second delay in all bits of port 310H.

79. 8255

80. Figure 11-11 8255 PPI Chip PROGRAMMING & INTERFACING THE 8255 The 8255 is a widely used It has three separately accessible programmed ports, A, B & C. Each port can be programmed to be input or output. Ports can also be changed dynamically. These 8-bit ports can be all input or all output. Port A (PA0–PA7) Port B (PB0–PB7) Port C (PC0–PC7)

81. PROGRAMMING & INTERFACING THE 8255 RD and WR - active-low 8255 control signal inputs. If the 8255 is using peripheral I/O, IOR & IOW of the system bus are connected to these two pins. If memory-mapped I/O, MEMR & MEMW activate them. RESET - an active-high signal input into the 8255, used to clear the control register. All ports are initialized as input ports.

82. These three pins are used to access ports A, B, C, or the control register. The control register must be programmed to select the operation mode of the three ports A, B, and C. PROGRAMMING & INTERFACING THE 8255 A0 , A1 , and CS CS (chip select) selects the entire chip. Address pins A0 and A1 select the specific port within the 8255.

83. 8255 Control Word Format (I/O Mode) PROGRAMMING & INTERFACING THE 8255 mode selection of the 8255A 8255 ports can be programmed in various modes. The simple I/O mode , Mode 0, is most widely used. Any of the ports A, B, CL & CU are programmable as input or output. All bits are out or all are in. No control of individual bits

84. PROGRAMMING & INTERFACING THE 8255 mode selection of the 8255A In simple mode, any of the ports A, B, CL, and CU can be programmed as input or output. All bits are out or all are in. No control of individual bits Programming of 8255 ports in simple I/O mode is illustrated in Examples 11-4, 11-5, and 11-6 on pages 301 -303 of your textbook.

85. PROGRAMMING & INTERFACING THE 8255 Visual C/C++ I/O programming There is no object or class for directly accessing I/O ports in the full Windows version of Visual C++. This precludes any hacking into the system hardware. This applies to Windows NT, 2000, XP, and higher. To access I/O and other hardware features of the x86 PC in the XP environment requires use of the Windows Platform SDK provided by Microsoft. Direct I/O addressing is available Windows 9x using Visual C++ in console mode.