Microprocessors and Controllers Chapter 3 8085 microprocessor.pdf
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Sep 25, 2024
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About This Presentation
Microprocessors and Controllers
Slide Content
MICROPROCESSORS AND CONTROLLERS
THE 8085 MICROPROCESSOR
THE 8085 MICROPROCESSOR
Architecture Of 8085 Microprocessor
It’s an 8-bit NMOS microprocessor
It’s available in the form of 40 Pin dual in line IC package.
It is fabricated on a single LSI chip.
It operates on +5 V d.c.supply.
The clock speed is about 3 MHZ.
It’s capable of addressing up to 64 K bytes (i.e. 216 = 65536 bytes) of memory.
The main functional components of 8085A microprocessor are as given below:
Register Section
Arithmetic and Logic Unit
Timing and Control Section
Interrupt Control
Serial Input / Output Control
It’s an 8-bit NMOS microprocessor
It’s available in the form of 40 Pin dual in line IC package.
It is fabricated on a single LSI chip.
It operates on +5 V d.c.supply.
The clock speed is about 3 MHZ.
It’s capable of addressing up to 64 K bytes (i.e. 216 = 65536 bytes) of memory.
The main functional components of 8085A microprocessor are as given below:
Register Section
Arithmetic and Logic Unit
Timing and Control Section
Interrupt Control
Serial Input / Output Control
Functional Block Diagram
Registers …
The 8085 microprocessor contains eight addressable 8-bit registers namely:
A (Accumulator) register
F Flag register (Flag flip-flops)
B, C, D, E, H,L register
These registers can either be used as single register or a combination of two
registers as 16 bit register pair (B-C, D-E or H-L)
The H-L register pair can also be used for register indirect addressing; since this
register pair can also function as data pointer.
The 8085 has remaining two 8-bit registers Accumulator (A) and Flag (F) as
special purpose registers and two 16 bit registers namely Program counter (PC)
and stack pointer (SP).
The 8085 microprocessor contains eight addressable 8-bit registers namely:
A (Accumulator) register
F Flag register (Flag flip-flops)
B, C, D, E, H,L register
These registers can either be used as single register or a combination of two
registers as 16 bit register pair (B-C, D-E or H-L)
The H-L register pair can also be used for register indirect addressing; since this
register pair can also function as data pointer.
The 8085 has remaining two 8-bit registers Accumulator (A) and Flag (F) as
special purpose registers and two 16 bit registers namely Program counter (PC)
and stack pointer (SP).
Registers …
… Registers…
Accumulator (A)
Accumulator is a 8 bit buffer register extensively used in arithmetic, logic, load and store
operations as well as in input / output instructions. All the arithmetic and logical operations are
performed on the accumulator contents
Flag (F) Register
It is an 8-bit register associated with the execution of instructions in the microprocessor. Out of
the 8 bits of flag register, 5 bits contains significant information in terms of status flags.
The five flags are:
Sign flag (S), Zero flag (Z), Carry flag (CY), Parity flag (P), Auxiliary Carry flag (AC)
The Accumulator and 8 bits (including three undefined bits) of flag register form a Program
Status Word (PSW).
The accumulator and flag registers are treated as a16 bit unit for stack operation.
Accumulator (A)
Accumulator is a 8 bit buffer register extensively used in arithmetic, logic, load and store
operations as well as in input / output instructions. All the arithmetic and logical operations are
performed on the accumulator contents
Flag (F) Register
It is an 8-bit register associated with the execution of instructions in the microprocessor. Out of
the 8 bits of flag register, 5 bits contains significant information in terms of status flags.
The five flags are:
Sign flag (S), Zero flag (Z), Carry flag (CY), Parity flag (P), Auxiliary Carry flag (AC)
The Accumulator and 8 bits (including three undefined bits) of flag register form a Program
Status Word (PSW).
The accumulator and flag registers are treated as a16 bit unit for stack operation.
… Registers…
… Registers
Program Counter –16 bit register
The program counter is a 16 bit register. It is used to send 16 bit address to fetch the instruction from the memory.
It acts as a pointer which indicates the address of the next instruction to be fetched and executed.
The program counter is updated after an instruction has been fetched by the processor.
Stack Pointer –16 bit register
The stack is an area of RAM (random access memory or read / write memory) in which temporary information is
stored.
It is stored on First-In-Last-Out (FILO) basis.
An address in the RAM area is assigned to the stack pointer where the first information is stored as the first stack
entry.
This is done by initializing stack pointer by an instruction.
Higher stack entries are made at the progressively decreasing addresses.
Program Counter –16 bit register
The program counter is a 16 bit register. It is used to send 16 bit address to fetch the instruction from the memory.
It acts as a pointer which indicates the address of the next instruction to be fetched and executed.
The program counter is updated after an instruction has been fetched by the processor.
Stack Pointer –16 bit register
The stack is an area of RAM (random access memory or read / write memory) in which temporary information is
stored.
It is stored on First-In-Last-Out (FILO) basis.
An address in the RAM area is assigned to the stack pointer where the first information is stored as the first stack
entry.
This is done by initializing stack pointer by an instruction.
Higher stack entries are made at the progressively decreasing addresses.
Address Buffer and Address-Data Buffer
More number of IC pins are required if separate address and data bus are
introduced.
To restrict the number of pins of 8085 to only 40, lower address lines A0-A7 and
data lines D0-D7 are used in multiplexed mode.
Themultiplexed lines are designed as Address/Data Bus (AD0-AD7).
Whenever 16-bit address is transmitted by the microprocessor 8 MSBs of the
address lines are sent on the Address Bus (A15-A8) and 8 LSBs of the lines are
sent on the Address/Data Bus (AD7-AD0).
The 8 LSBs of the address are then latched either into memory or external latch
so that the complete address remains available for further operation.
The 8-bit Address/Data Bus will now be free for the data transmission.
More number of IC pins are required if separate address and data bus are
introduced.
To restrict the number of pins of 8085 to only 40, lower address lines A0-A7 and
data lines D0-D7 are used in multiplexed mode.
Themultiplexed lines are designed as Address/Data Bus (AD0-AD7).
Whenever 16-bit address is transmitted by the microprocessor 8 MSBs of the
address lines are sent on the Address Bus (A15-A8) and 8 LSBs of the lines are
sent on the Address/Data Bus (AD7-AD0).
The 8 LSBs of the address are then latched either into memory or external latch
so that the complete address remains available for further operation.
The 8-bit Address/Data Bus will now be free for the data transmission.
Arithmetic and Logical Unit (ALU)
The arithmetic and logical unit (ALU) basically consists of accumulator (A), flag register (F) and a temporary register (which
is inaccessible by the programmer or user).
This unit carries out the arithmetic and logic calculations of the data stored in general purpose registers or in memory
locations. The arithmetic operations are ADD, SUB, compare, increments, decrements and complements etc.; while logical
operations are AND, OR, XOR and Rotate.
The result of these operations could be placed in the accumulator or elsewhere through the internal bus.
Arithmetic operations are usually carried out in 2’s complement adder / subtrator
Forthese operations, ALU receives the control signals from the timing and control unit.
The arithmetic and logical unit (ALU) basically consists of accumulator (A), flag register (F) and a temporary register (which
is inaccessible by the programmer or user).
This unit carries out the arithmetic and logic calculations of the data stored in general purpose registers or in memory
locations. The arithmetic operations are ADD, SUB, compare, increments, decrements and complements etc.; while logical
operations are AND, OR, XOR and Rotate.
The result of these operations could be placed in the accumulator or elsewhere through the internal bus.
Arithmetic operations are usually carried out in 2’s complement adder / subtrator
Forthese operations, ALU receives the control signals from the timing and control unit.
Timing and Control Unit
This unit consists of the following sections:
Instruction Register and Decoder
Control signals
Instruction Register and Decoder
The CPU fetches an instruction from the memory for its execution.
This instruction can be of 1-3 byte long.
The first byte contains the op code of instruction which basically specifies the nature of operation to be performed indicating
the length of the instruction.
The first byte (op code of the instruction) transferred to 8-bit instruction register through the internal bus of the CPU, becomes
available at the instruction decoder.
The decoder decodes the op code and directs the control unit to produce the necessary control signals.
This unit consists of the following sections:
Instruction Register and Decoder
Control signals
Instruction Register and Decoder
The CPU fetches an instruction from the memory for its execution.
This instruction can be of 1-3 byte long.
The first byte contains the op code of instruction which basically specifies the nature of operation to be performed indicating
the length of the instruction.
The first byte (op code of the instruction) transferred to 8-bit instruction register through the internal bus of the CPU, becomes
available at the instruction decoder.
The decoder decodes the op code and directs the control unit to produce the necessary control signals.
Timing and Control Unit…
Control Signals
(i) X1, X2 and CLK Out
Two pins X1 and X2 are provided to be externally connected to a quartz crystal.
The quartz crystal of 6.144 MHz is used in this processor.
This gives the clock frequency of 3.072 MHz (half of the crystal frequency) of 50% duty cycle.
The output of the clock frequency is also available at CLK out terminal.
(ii) Address Latch Enable (ALE)
The 16 bit address bus is basically divided into two sets (A8-A15and AD0-AD7)
The AD0-AD7 is used as address bus, during the first clock cycle of the machine cycle
involving memory; and during the remaining clock cycle of the machine cycle, it acts as the
data bus.
This is accomplished by address latch enable (ALE) signal provided in the processor.
During the first clock cycle of the machine cycle ALE is high which enables the lower 8-bit of
the address to be latched either into the memory or external latch.
Control Signals
(i) X1, X2 and CLK Out
Two pins X1 and X2 are provided to be externally connected to a quartz crystal.
The quartz crystal of 6.144 MHz is used in this processor.
This gives the clock frequency of 3.072 MHz (half of the crystal frequency) of 50% duty cycle.
The output of the clock frequency is also available at CLK out terminal.
(ii) Address Latch Enable (ALE)
The 16 bit address bus is basically divided into two sets (A8-A15and AD0-AD7)
The AD0-AD7 is used as address bus, during the first clock cycle of the machine cycle
involving memory; and during the remaining clock cycle of the machine cycle, it acts as the
data bus.
This is accomplished by address latch enable (ALE) signal provided in the processor.
During the first clock cycle of the machine cycle ALE is high which enables the lower 8-bit of
the address to be latched either into the memory or external latch.
… Timing and Control Unit…
(iii)�
�(Read ) Signal
This is an active low signal to be connected to memory read input (output enable
signal to memories) or to input / output read signal to enable input / output buffer.
(iv) ??????
�(Write) Signal
Similar to read signal, write signal is also active low.
This signal is used to write to the memory or input / output devices.
(v) IO/�(Input Output / Memory)
This signal distinguishes that the address and data is meant for either I/O devices
or memory.
Whenever this signal is high (1), microprocessor will communicate to the I/O
devices and whenever it is low (0), microprocessor will communicate to the
memory.
(iii)�
�(Read ) Signal
This is an active low signal to be connected to memory read input (output enable
signal to memories) or to input / output read signal to enable input / output buffer.
(iv) ??????
�(Write) Signal
Similar to read signal, write signal is also active low.
This signal is used to write to the memory or input / output devices.
(v) IO/�(Input Output / Memory)
This signal distinguishes that the address and data is meant for either I/O devices
or memory.
Whenever this signal is high (1), microprocessor will communicate to the I/O
devices and whenever it is low (0), microprocessor will communicate to the
memory.
… Timing and Control Unit…
(vi) Status Signals (S0, S1)
The status signals (S0, S1) along with IO/M signal indicate the type of machine cycle in progress.
The type of machine cycle are op code fetch cycle, memory read cycle, memory write cycle, I/O read cycle or I/O
write cycle.
(vi) Status Signals (S0, S1)
The status signals (S0, S1) along with IO/M signal indicate the type of machine cycle in progress.
The type of machine cycle are op code fetch cycle, memory read cycle, memory write cycle, I/O read cycle or I/O
write cycle.
… Timing and Control Unit…
(vii) Hold and HLDA
HOLD and HLDA (Hold Acknowledge) signals are used for DMA (Direct Memory Access)
operation.
The transfer of data directly from I/O devices to memory without involvement of
microprocessor is called DMA.
The DMA will save the time as CPU relinquishes the control of Buses.
The HOLD and HLDA signals are used in the operation.
Whenever HOLD signal is high, CPU temporarily relinquishes its operation by floating the
address, data and control buses; and DMA operation is started.
A high HLDA (Hold Acknowledge) signal is also sent to DMA controller, indicating that CPU
has received the hold request.
Whenever the data transfer is complete, then the control to CPU is returned back.
Further the HLDA signal goes low.
(vii) Hold and HLDA
HOLD and HLDA (Hold Acknowledge) signals are used for DMA (Direct Memory Access)
operation.
The transfer of data directly from I/O devices to memory without involvement of
microprocessor is called DMA.
The DMA will save the time as CPU relinquishes the control of Buses.
The HOLD and HLDA signals are used in the operation.
Whenever HOLD signal is high, CPU temporarily relinquishes its operation by floating the
address, data and control buses; and DMA operation is started.
A high HLDA (Hold Acknowledge) signal is also sent to DMA controller, indicating that CPU
has received the hold request.
Whenever the data transfer is complete, then the control to CPU is returned back.
Further the HLDA signal goes low.
… Timing and Control Unit
(viii) READY signal (Input)
Some peripheral devices connected to 8085 microprocessor operate at much slower speed than the processor.
To synchronize the speed of CPU and peripheral devices or to slow down the speed of 8085, the READY signal is
used.
If the READY signal is high the peripheral device is ready and the processor can complete the data transfer.
If this signal is low the microprocessor waits (by generating a number of NOP T-states) till it goes high.
(ix) �������and RESET OUT
The �������signal may be low from the operator Reset button or from the processor.
When the signal is low, the CPU will reset the program counter, instruction register and other circuits.
It also sends a high RESET OUT.
The RESET OUT signal goes to peripheral devices to reset or initialize them.
When �������signal goes high and RESET OUT goes low, the data processing may begin.A
(viii) READY signal (Input)
Some peripheral devices connected to 8085 microprocessor operate at much slower speed than the processor.
To synchronize the speed of CPU and peripheral devices or to slow down the speed of 8085, the READY signal is
used.
If the READY signal is high the peripheral device is ready and the processor can complete the data transfer.
If this signal is low the microprocessor waits (by generating a number of NOP T-states) till it goes high.
(ix) �������and RESET OUT
The �������signal may be low from the operator Reset button or from the processor.
When the signal is low, the CPU will reset the program counter, instruction register and other circuits.
It also sends a high RESET OUT.
The RESET OUT signal goes to peripheral devices to reset or initialize them.
When �������signal goes high and RESET OUT goes low, the data processing may begin.A
Interrupt Control
Sometimes it is necessary to interrupt the execution of the main program.
For this an interrupt request is obtained from the I/O devices.
After receiving the interrupt request, processor temporarily stops what it was doing and attends to the I/O device.
����is an interrupt acknowledge signal which is sent by the microprocessor after INTR signal is received.
After the work of the I/O device is complete it returns to what it was doing earlier.
Basically 8085A has five hardware interrupts namely: INTR, RST 5.5,RST 6.5, RST 7.5, TRAP
If two or more of these interrupts are active at the same time, the 8085 takes them in order of priority level.
Sometimes it is necessary to interrupt the execution of the main program.
For this an interrupt request is obtained from the I/O devices.
After receiving the interrupt request, processor temporarily stops what it was doing and attends to the I/O device.
����is an interrupt acknowledge signal which is sent by the microprocessor after INTR signal is received.
After the work of the I/O device is complete it returns to what it was doing earlier.
Basically 8085A has five hardware interrupts namely: INTR, RST 5.5,RST 6.5, RST 7.5, TRAP
If two or more of these interrupts are active at the same time, the 8085 takes them in order of priority level.
Serial I/O Control
Serial input / output control circuit incorporated in this microprocessor is used for
the data transmission.
For this purpose two pins SID and SOD are provided in the serial input/output
control unit.
The SID (Serial Input Data) terminal receives the serial data stream from an input
device, the control unit converts serial data stream to parallel data before it is
used by the computer.
After the conversion 8-bit parallel data is stored in the accumulator.
Similarly, SOD (Serial Out Data) terminal outputs the 8-bit parallel available
with the accumulator into serial form to the peripheral device connected with the
computer.
Serial input / output control circuit incorporated in this microprocessor is used for
the data transmission.
For this purpose two pins SID and SOD are provided in the serial input/output
control unit.
The SID (Serial Input Data) terminal receives the serial data stream from an input
device, the control unit converts serial data stream to parallel data before it is
used by the computer.
After the conversion 8-bit parallel data is stored in the accumulator.
Similarly, SOD (Serial Out Data) terminal outputs the 8-bit parallel available
with the accumulator into serial form to the peripheral device connected with the
computer.
Pin Description Of 8085 …
… Pin Description Of 8085 …
… Pin Description Of 8085 …
PIN 1 and 2
These X1 and X2 pins are to be connected to an external quartz crystal, L-C or R-C network which drives the
internal clock generator.
Generally, quartz crystal is used for the On-chip oscillator for the accurate and stable clock frequency.
The network produces a signal whose frequency tolerance is about ±10%.
PIN 1 and 2
These X1 and X2 pins are to be connected to an external quartz crystal, L-C or R-C network which drives the
internal clock generator.
Generally, quartz crystal is used for the On-chip oscillator for the accurate and stable clock frequency.
The network produces a signal whose frequency tolerance is about ±10%.
… Pin Description Of 8085 …
PIN 3
This is RESET OUT signal, which indicates that CPU is being reset.
When it is high, system is reset.
The signal is synchronized to the processor clock and lasts for an integral number for clock periods. When the RESET OUT
signal goes low, the processing begins.
PIN 4 and 5
Pin 4 and 5 indicate SOD (Serial Out Data) and SID (Serial In Data) terminals respectively.
These pins are associated with Serial Input/Outputcontrol unit for 8085 microprocessor.
On executing SIM (Set Interrupt Mask) instruction, if bit D6 is set to 1, the content of D7 bit (set or reset) of the accumulator is
latched on the SOD pin.
The data on the SID line (PIN 5) loads into accumulator at bit D7 whenever a RIM instruction is executed
PIN 3
This is RESET OUT signal, which indicates that CPU is being reset.
When it is high, system is reset.
The signal is synchronized to the processor clock and lasts for an integral number for clock periods. When the RESET OUT
signal goes low, the processing begins.
PIN 4 and 5
Pin 4 and 5 indicate SOD (Serial Out Data) and SID (Serial In Data) terminals respectively.
These pins are associated with Serial Input/Outputcontrol unit for 8085 microprocessor.
On executing SIM (Set Interrupt Mask) instruction, if bit D6 is set to 1, the content of D7 bit (set or reset) of the accumulator is
latched on the SOD pin.
The data on the SID line (PIN 5) loads into accumulator at bit D7 whenever a RIM instruction is executed
… Pin Description Of 8085 …
PIN 6 to 11
The interrupt control unit of the microprocessor contains these pins.
The Pins 6 to 11 are restart interrupts named as:
TRAP (Pin No.6) I Priority
RST 7.5 (Pin No. 7) II Priority
RST 6.5 (Pin No. 8) III Priority
RST 5.5 (Pin No. 9) IV Priority
INTR (Pin No. 10) V Priority
The TRAP has the highest priority and INTR has the lowest priority.
TheTRAP is non-maskableinterrupt.
It is both edge and level sensitive.
The interrupts (TRAP, RST 7.5, RST 6.5 and RST 5.5) are also called vector interrupts, as each interrupt has fixed
memory location (vector location) for the transfer of control from the normal execution of the routine.
PIN 6 to 11
The interrupt control unit of the microprocessor contains these pins.
The Pins 6 to 11 are restart interrupts named as:
TRAP (Pin No.6) I Priority
RST 7.5 (Pin No. 7) II Priority
RST 6.5 (Pin No. 8) III Priority
RST 5.5 (Pin No. 9) IV Priority
INTR (Pin No. 10) V Priority
The TRAP has the highest priority and INTR has the lowest priority.
TheTRAP is non-maskableinterrupt.
It is both edge and level sensitive.
The interrupts (TRAP, RST 7.5, RST 6.5 and RST 5.5) are also called vector interrupts, as each interrupt has fixed
memory location (vector location) for the transfer of control from the normal execution of the routine.
… Pin Description Of 8085 …
As soon as any of these pins 6 to 10 are active (high), the internal circuit of 8085 stops the
normal execution of program and the program control is transferred to the corresponding
memory location (vector location).
INTR (Pin 10) is a general purpose interrupt and has the lowest priority.
As soon as Pin 10 is high, the microprocessor stops the execution of normal program and after
completing the instruction at hand, it goes to CALL instruction.
The INTR is enabled or disabled by the instructions ET (Enable Interrupts) or DI (Disable
Interrupts) respectively.
The Pin 11 is an Interrupt Acknowledge ( ����) signal.
A low (logic 0) to this pin indicate that the microprocessor has acknowledged the request from
the peripheral device.
It is also used to activate the interrupt controller.
As soon as any of these pins 6 to 10 are active (high), the internal circuit of 8085 stops the
normal execution of program and the program control is transferred to the corresponding
memory location (vector location).
INTR (Pin 10) is a general purpose interrupt and has the lowest priority.
As soon as Pin 10 is high, the microprocessor stops the execution of normal program and after
completing the instruction at hand, it goes to CALL instruction.
The INTR is enabled or disabled by the instructions ET (Enable Interrupts) or DI (Disable
Interrupts) respectively.
The Pin 11 is an Interrupt Acknowledge ( ����) signal.
A low (logic 0) to this pin indicate that the microprocessor has acknowledged the request from
the peripheral device.
It is also used to activate the interrupt controller.
… Pin Description Of 8085 …
PIN 12 to 19
Pin 12 to 19 (AD0-AD7) form bi-directional multiplexed Address/Data Bus.
The least significant 8 bits of the memory address (or I/O Address) appear on the bus during the first T-states of a machine
cycle.
It then becomes the data bus during the next T-states.
PIN 20
Pin 20 is the ground terminal.
PIN 21 to 28
The Pin 21 to 28 (A8-A15) form unidirectional most significant 8 bits of memory address or 8 bits of the I/O address.
It remains in the high impedance state during HOLD, HALT and RESET modes.
PIN 29 to 33
The Pin 29 to 33 labelled as S0 and S1 respectively are known as status signals.
These status signals along with IO/M signal indicate the various operations.
PIN 12 to 19
Pin 12 to 19 (AD0-AD7) form bi-directional multiplexed Address/Data Bus.
The least significant 8 bits of the memory address (or I/O Address) appear on the bus during the first T-states of a machine
cycle.
It then becomes the data bus during the next T-states.
PIN 20
Pin 20 is the ground terminal.
PIN 21 to 28
The Pin 21 to 28 (A8-A15) form unidirectional most significant 8 bits of memory address or 8 bits of the I/O address.
It remains in the high impedance state during HOLD, HALT and RESET modes.
PIN 29 to 33
The Pin 29 to 33 labelled as S0 and S1 respectively are known as status signals.
These status signals along with IO/M signal indicate the various operations.
… Pin Description Of 8085 …
… Pin Description Of 8085 …
PIN 30
The Pin 30 is known as ALE (Address Latch Enable) terminal.
When this signal is high the information carried on the multiplexed address/data bus (AD0-AD7) is the lower 8
bits of the address.
It also enables the low order address (AD0-AD7) from the multiplexed address/data bus to latch either into the
memory or the external latch.
PIN 31, 32 and 34
The Pin 31 and 32 are the two control signals �
�and �
??????respectively.
The pin 34 carries IO/�signal which is one of the status signals.
The other status signals are S0 and S1 discussed earlier.
A low �
�signal generated by the microprocessor sends (writes) data into I/O devices or memory.
Similarly, a low �
??????signal generated by the microprocessor reads (receives) the data from the I/O devices or
memory locations.
The IO/�signal indicates whether the address on the address bus is meant for I/O devices.
However, a low to this signal indicates that the address on the address bus is meant for memory location.
The �
�, �
??????and IO/�signals function together.
PIN 30
The Pin 30 is known as ALE (Address Latch Enable) terminal.
When this signal is high the information carried on the multiplexed address/data bus (AD0-AD7) is the lower 8
bits of the address.
It also enables the low order address (AD0-AD7) from the multiplexed address/data bus to latch either into the
memory or the external latch.
PIN 31, 32 and 34
The Pin 31 and 32 are the two control signals �
�and �
??????respectively.
The pin 34 carries IO/�signal which is one of the status signals.
The other status signals are S0 and S1 discussed earlier.
A low �
�signal generated by the microprocessor sends (writes) data into I/O devices or memory.
Similarly, a low �
??????signal generated by the microprocessor reads (receives) the data from the I/O devices or
memory locations.
The IO/�signal indicates whether the address on the address bus is meant for I/O devices.
However, a low to this signal indicates that the address on the address bus is meant for memory location.
The �
�, �
??????and IO/�signals function together.
… Pin Description Of 8085 …
PIN 35
The Pin 35 is known as READY signal which forces the microprocessor to wait till the data become available
from the memory or input/output devices.
This signal is needed to synchronize the speed of the microprocessor with I/O devices or memory as the memory
or I/O devices are not as fast as the microprocessor.
When the READY signal is low, the microprocessor waits till the READY signal is 1. As soon as READY signal
is 1, the microprocessor knows that the data are available from the memory or I/O devices.
PIN 36
This pin �������is signal.
This input carrying signal may be operated by the operator using the RESET button provided externally or it may
be operated directly from the other source.
When this signal is low (momentarily), the CPU will reset the program counter, instruction register, all interrupts
(except TRAP) are disabled, SOD signal becomes low and Data, address and control buses are floated.
When this signal goes high, the data processing begins.
PIN 35
The Pin 35 is known as READY signal which forces the microprocessor to wait till the data become available
from the memory or input/output devices.
This signal is needed to synchronize the speed of the microprocessor with I/O devices or memory as the memory
or I/O devices are not as fast as the microprocessor.
When the READY signal is low, the microprocessor waits till the READY signal is 1. As soon as READY signal
is 1, the microprocessor knows that the data are available from the memory or I/O devices.
PIN 36
This pin �������is signal.
This input carrying signal may be operated by the operator using the RESET button provided externally or it may
be operated directly from the other source.
When this signal is low (momentarily), the CPU will reset the program counter, instruction register, all interrupts
(except TRAP) are disabled, SOD signal becomes low and Data, address and control buses are floated.
When this signal goes high, the data processing begins.
… Pin Description Of 8085
PIN 37
This pin carries CLK OUT signal.
It is derived from the on-chip oscillator, which goes to peripherals to synchronize their timings.
PIN 38-39
The Pin 38 and 39 are the HOLD and HLDA (Hold Acknowledge) signals respectively.
These signals are used in DMA (Direct Memory Access) operations.
When any I/O device indicates that the data are ready for DMA transfer, a high HOLD signal is sent by the DMA controller to
the 8085 microprocessor.
It is in fact a request signal from the DMA controller to the microprocessor.
The microprocessor then sends a high signal to DMA controller indicating that the microprocessor has received the request
from the I/O devices and will relinquish the address, data and control bus after completing the current instruction.
The DMA controller thus carries out the data transfer.
A low HOLD signal will return the control to the microprocessor.
PIN 40
The pin 40 is +VCC, which is to be externally connected to +5 volt D.C. supply.
PIN 37
This pin carries CLK OUT signal.
It is derived from the on-chip oscillator, which goes to peripherals to synchronize their timings.
PIN 38-39
The Pin 38 and 39 are the HOLD and HLDA (Hold Acknowledge) signals respectively.
These signals are used in DMA (Direct Memory Access) operations.
When any I/O device indicates that the data are ready for DMA transfer, a high HOLD signal is sent by the DMA controller to
the 8085 microprocessor.
It is in fact a request signal from the DMA controller to the microprocessor.
The microprocessor then sends a high signal to DMA controller indicating that the microprocessor has received the request
from the I/O devices and will relinquish the address, data and control bus after completing the current instruction.
The DMA controller thus carries out the data transfer.
A low HOLD signal will return the control to the microprocessor.
PIN 40
The pin 40 is +VCC, which is to be externally connected to +5 volt D.C. supply.
Instruction Set Of 8085 Microprocessor
The instruction set of 8085 can be classified into following
groups.
1. Data Transfer Group
2. Arithmetic Group
3. Branch Group
4. Stack, Input/Outputand Machine Control Group
The instruction set of 8085 can be classified into following
groups.
1. Data Transfer Group
2. Arithmetic Group
3. Branch Group
4. Stack, Input/Outputand Machine Control Group
Data Transfer Group …
The function of data transfer group of instructions is to transfer the data
from register to register, register to memory and also immediate
transfer of data (given) to memory location.
These data transfer instructions can further be subdivided on the basis
of modes of addressing i.e. direct, immediate and register addressing.
No Flag affected
The function of data transfer group of instructions is to transfer the data
from register to register, register to memory and also immediate
transfer of data (given) to memory location.
These data transfer instructions can further be subdivided on the basis
of modes of addressing i.e. direct, immediate and register addressing.
No Flag affected
… Data Transfer Group …
Direct Data Transfer Instructions
three byte instruction
LDA address; �←[�
address
]
For example if 2AH data is stored in memory location 2500H before the execution of LDA
2500Hinstruction, then after the execution of this instruction, the data 2AH will be transferred
to accumulator. �←2�
STA address ; �
address
←[�]
For example if 16H data is stored in the accumulator before the execution of STA 2100H
instruction, then after the execution of this instruction, the data 16H will be transferred to the
addressed memory location. �
2100
←16
Direct Data Transfer Instructions
three byte instruction
LDA address; �←[�
address
]
For example if 2AH data is stored in memory location 2500H before the execution of LDA
2500Hinstruction, then after the execution of this instruction, the data 2AH will be transferred
to accumulator. �←2�
STA address ; �
address
←[�]
For example if 16H data is stored in the accumulator before the execution of STA 2100H
instruction, then after the execution of this instruction, the data 16H will be transferred to the
addressed memory location. �
2100
←16
… Data Transfer Group …
LHLD address ; �←[�
address
], �←[�
address+1
]
SHLD address; �
address
←[�], �
address+1
←[�]
LDAX rp; �←[�rp]
The H-L register pair is not included in this instruction.
STAX rp; �rp←[�]
XCHG; �↔�,[�]↔[�]
Let us write a program to add two numbers stored in memory locations 2100 H and 2201 H without using LDAX
and STAX instructions. The answer is to be loaded in the memory location 2100 H.
LXI H, 2201 H ; Loads H = 22 H and L = 01 H
LXI D, 2100 H ; Loads D = 21 H and E = 00 H
MOV A, M ; �←[�
2201
]
XCHG ; H = 21 H, L = 00 H and D = 22 H, E = 01 H
ADD M; �←�+ [�
2100]
MOV M, A ; [�
2100]←�
HLT
In this program no LDAX and STAX instructions are used.
LHLD address ; �←[�
address
], �←[�
address+1
]
SHLD address; �
address
←[�], �
address+1
←[�]
LDAX rp; �←[�rp]
The H-L register pair is not included in this instruction.
STAX rp; �rp←[�]
XCHG; �↔�,[�]↔[�]
Let us write a program to add two numbers stored in memory locations 2100 H and 2201 H without using LDAX
and STAX instructions. The answer is to be loaded in the memory location 2100 H.
LXI H, 2201 H ; Loads H = 22 H and L = 01 H
LXI D, 2100 H ; Loads D = 21 H and E = 00 H
MOV A, M ; �←[�
2201
]
XCHG ; H = 21 H, L = 00 H and D = 22 H, E = 01 H
ADD M; �←�+ [�
2100]
MOV M, A ; [�
2100]←�
HLT
In this program no LDAX and STAX instructions are used.
… Data Transfer Group …
Register Data Transfer Instructions
These instructions transfer 8-bit data stored in one register to other register.
One byte instruction
MOV reg1, reg2
reg1 = A, B, C, D, E, H or L and reg2 = A, B, C, D, E, H or L
It copies (transfers) the content stored in reg2 to reg1.[���1]←[���2]
MOV D, D MOV A, C MOV L, D …
For example if L = 23 H before the execution of instruction MOV C, L then after
the execution of this instruction 23 H data in register L will be transferred to
register C. [�]←23�
Register Data Transfer Instructions
These instructions transfer 8-bit data stored in one register to other register.
One byte instruction
MOV reg1, reg2
reg1 = A, B, C, D, E, H or L and reg2 = A, B, C, D, E, H or L
It copies (transfers) the content stored in reg2 to reg1.[���1]←[���2]
MOV D, D MOV A, C MOV L, D …
For example if L = 23 H before the execution of instruction MOV C, L then after
the execution of this instruction 23 H data in register L will be transferred to
register C. [�]←23�
… Data Transfer Group …
Register Indirect Data Transfer Instructions
one byte instruction
There are some register indirect data transfer instructions in which H-L register pair acts like ‘data pointer’.
The data pointer is represented by M which denotes the memory location whose address is given in the H-L
register pair. It is basically represented by �
HL.
For example HL = 2500 H thenM ⇒�
HLrepresents the memory location whose address is 2500 H.
It indicates the memory location �
2500.
MOV reg, M ; ??????????????????←�
HL
reg= A, B, C, D, E, H or L
This instruction is indirect read instruction. It moves / copies the data stored in memory location whose address is
given in H-L register pair, to the given register.
E.g, Consider 12H data is stored in the memory location whose address is given in H-L register pair (i.e. H-L =
2500H). After the execution of the instruction MOV B, M the data 12H will be stored in B register. [�]←12
MOV M, reg; �
HL←??????????????????
This instruction moves / copies the data in the given register to the memory location addressed by H-L register
pair.
For example let D = 4EH, H = 23H, L = 00H, Then after execution of the instruction MOV M, D will produce the
result: �
HL←4�
Register Indirect Data Transfer Instructions
one byte instruction
There are some register indirect data transfer instructions in which H-L register pair acts like ‘data pointer’.
The data pointer is represented by M which denotes the memory location whose address is given in the H-L
register pair. It is basically represented by �
HL.
For example HL = 2500 H thenM ⇒�
HLrepresents the memory location whose address is 2500 H.
It indicates the memory location �
2500.
MOV reg, M ; ??????????????????←�
HL
reg= A, B, C, D, E, H or L
This instruction is indirect read instruction. It moves / copies the data stored in memory location whose address is
given in H-L register pair, to the given register.
E.g, Consider 12H data is stored in the memory location whose address is given in H-L register pair (i.e. H-L =
2500H). After the execution of the instruction MOV B, M the data 12H will be stored in B register. [�]←12
MOV M, reg; �
HL←??????????????????
This instruction moves / copies the data in the given register to the memory location addressed by H-L register
pair.
For example let D = 4EH, H = 23H, L = 00H, Then after execution of the instruction MOV M, D will produce the
result: �
HL←4�
… Data Transfer Group
Immediate Data Transfer Instructions
two byte instructions
MVI reg, data ; [���]←����
E.g1 MVI E, 1AH ; [�]←1�
E.g2 If H = 21 H L = 00 H then
MVI M, 2BH ; �
2100
←2�
Immediate Data Transfer Instructions
two byte instructions
MVI reg, data ; [���]←����
E.g1 MVI E, 1AH ; [�]←1�
E.g2 If H = 21 H L = 00 H then
MVI M, 2BH ; �
2100
←2�
Arithmetic Group of Instructions …
Add instructions
All the flags are affected with this instruction except in DAD.
ADD reg; [�]←[�]+[���]
E.gSuppose before the execution of the instruction ADD E
A = 10101111, E = 10110101, CY = 0 , S = 1, Z = 0 and P = 1
then after the execution of the instruction ADD E we get the following result:
A = 1 0 1 0 1 1 1 1
E = 1 0 1 1 0 1 0 1
A = 1 0 1 1 0 0 1 0 0
CY
The flags will be affected as;
CY = 1, S = 0 , Z = 0 and P = 0
Add instructions
All the flags are affected with this instruction except in DAD.
ADD reg; [�]←[�]+[���]
E.gSuppose before the execution of the instruction ADD E
A = 10101111, E = 10110101, CY = 0 , S = 1, Z = 0 and P = 1
then after the execution of the instruction ADD E we get the following result:
A = 1 0 1 0 1 1 1 1
E = 1 0 1 1 0 1 0 1
A = 1 0 1 1 0 0 1 0 0
CY
The flags will be affected as;
CY = 1, S = 0 , Z = 0 and P = 0
… Arithmetic Group of Instructions …
ADD M ; ??????←??????+�
��
E.g let A = 40 H H = 21 H-L = 00 H and M
2100= 3AH
Then after execution of the instruction ADD M will produce the result: A = 7A H
All flag will, however, be affected as per the instruction.
ADI data; [�]←[�]+����
ADC reg; [�]←[�]+[���]+[��]
E.gSuppose before the execution of the instruction ADC D
A = 10101001, D = 10111101, CY = 1, S = 1, Z = 0 and P = 1
then after the execution of the instruction ADC D we get the following result:
CY = 1
A = 1 0 1 0 1 0 0 1
D = 1 0 1 1 1 1 0 1
A = 1 0 1 1 0 0 1 1 1
CY
ADD M ; ??????←??????+�
��
E.g let A = 40 H H = 21 H-L = 00 H and M
2100= 3AH
Then after execution of the instruction ADD M will produce the result: A = 7A H
All flag will, however, be affected as per the instruction.
ADI data; [�]←[�]+����
ADC reg; [�]←[�]+[���]+[��]
E.gSuppose before the execution of the instruction ADC D
A = 10101001, D = 10111101, CY = 1, S = 1, Z = 0 and P = 1
then after the execution of the instruction ADC D we get the following result:
CY = 1
A = 1 0 1 0 1 0 0 1
D = 1 0 1 1 1 1 0 1
A = 1 0 1 1 0 0 1 1 1
CY
… Arithmetic Group of Instructions …
ADC M; �←�+�
????????????+��
E.g let A = 50 H, CY = 1, H = 25 H, L = 00 H and M
2500= 3BH
Then after execution of the instruction ADC M will produce the result: A = 8C H
All flag will, however, be affected as per the result.
ACI data; [�]←[�]+����+��
DAD rp;[��]←[��]+[��]
where rpstands for register pair.
It may be B, D or H. B represents B-C register pair, D represents D-E register pair, H represents H-L register pair.
For example before the execution of the instruction DAD D, we have the following data in different registers.
DE = 2AB6 H, HL = 0127 H
After the execution of this instruction we HL = 2BDD H
Only carry flag will be affected in this instruction.
ADC M; �←�+�
????????????+��
E.g let A = 50 H, CY = 1, H = 25 H, L = 00 H and M
2500= 3BH
Then after execution of the instruction ADC M will produce the result: A = 8C H
All flag will, however, be affected as per the result.
ACI data; [�]←[�]+����+��
DAD rp;[��]←[��]+[��]
where rpstands for register pair.
It may be B, D or H. B represents B-C register pair, D represents D-E register pair, H represents H-L register pair.
For example before the execution of the instruction DAD D, we have the following data in different registers.
DE = 2AB6 H, HL = 0127 H
After the execution of this instruction we HL = 2BDD H
Only carry flag will be affected in this instruction.
… Arithmetic Group of Instructions …
DAA
The DAA is one byte instruction and no operand is needed with this instruction.
Itadjusts the accumulator to packed BCD (Binary Coded Decimal) after addition of two BCDs.
In other words, after addition of two hexadecimal numbers if this instruction is used then the
result in decimal form is obtained.
For this Auxiliary Carry Flag (AC) and Carry Flag (CY) take care of this instruction.
It functions in two steps:
1. If the lower nibble (lower 4-bits) of the accumulator is greater than 9 or Auxiliary carry flag
is set, then it adds 06 H to the accumulator.
2. Subsequently, if the higher nibble (higher 4-bits) of the accumulator is now greater than 9 or
the carry flag (CY) is set, it adds 60 H to the accumulator.
All the flags are affected with this instruction.
DAA
The DAA is one byte instruction and no operand is needed with this instruction.
Itadjusts the accumulator to packed BCD (Binary Coded Decimal) after addition of two BCDs.
In other words, after addition of two hexadecimal numbers if this instruction is used then the
result in decimal form is obtained.
For this Auxiliary Carry Flag (AC) and Carry Flag (CY) take care of this instruction.
It functions in two steps:
1. If the lower nibble (lower 4-bits) of the accumulator is greater than 9 or Auxiliary carry flag
is set, then it adds 06 H to the accumulator.
2. Subsequently, if the higher nibble (higher 4-bits) of the accumulator is now greater than 9 or
the carry flag (CY) is set, it adds 60 H to the accumulator.
All the flags are affected with this instruction.
… Arithmetic Group of Instructions …
Subtract Instructions
SUB reg; [�]←[�]−[���]
All the flags are affected with this ‘SUB reg’ instruction.
Suppose before the execution of the instruction SUB D
A = 10101111, D = 10110101, CY = 0 , S = 1, Z = 0 and P = 1then after the
execution of the instruction SUB D we get the following result:
A = 1 0 1 0 1 1 1 1
D = 1 0 1 1 0 1 0 1
A = 1 1 1 1 1 1 0 1 0
CY
All flags will be affected as per the accumulator contents.
Subtract Instructions
SUB reg; [�]←[�]−[���]
All the flags are affected with this ‘SUB reg’ instruction.
Suppose before the execution of the instruction SUB D
A = 10101111, D = 10110101, CY = 0 , S = 1, Z = 0 and P = 1then after the
execution of the instruction SUB D we get the following result:
A = 1 0 1 0 1 1 1 1
D = 1 0 1 1 0 1 0 1
A = 1 1 1 1 1 1 0 1 0
CY
All flags will be affected as per the accumulator contents.
… Arithmetic Group of Instructions …
SUB M;�←�−�
????????????
In this instruction too all flags are affected.
For example let A = 56H, H=22H, L = 01 H and M
2201= 2CH
Then after execution of the instruction SUB M will produce the result: A = 2A H
SUI data ; [�]←[�]−����
All flags will be affected with this instruction.
SUB M;�←�−�
????????????
In this instruction too all flags are affected.
For example let A = 56H, H=22H, L = 01 H and M
2201= 2CH
Then after execution of the instruction SUB M will produce the result: A = 2A H
SUI data ; [�]←[�]−����
All flags will be affected with this instruction.
… Arithmetic Group of Instructions …
SBB reg; [�]←[�]−[���]−[��]
All the flags are affected in the operation of this instruction.
Suppose before the execution of the instruction SBB H
A = 10101111, H = 10110101, CY = 0 , S = 1, Z = 0 and P = 1
then after the execution of the instruction SUB H we get the following result:
A = 1 0 1 0 1 1 1 1
H = 1 0 1 1 0 1 0 1
CY = 1
A = 1 1 1 1 1 1 0 0 1
CY
SBB reg; [�]←[�]−[���]−[��]
All the flags are affected in the operation of this instruction.
Suppose before the execution of the instruction SBB H
A = 10101111, H = 10110101, CY = 0 , S = 1, Z = 0 and P = 1
then after the execution of the instruction SUB H we get the following result:
A = 1 0 1 0 1 1 1 1
H = 1 0 1 1 0 1 0 1
CY = 1
A = 1 1 1 1 1 1 0 0 1
CY
… Arithmetic Group of Instructions
SBB M; �←�−�
????????????−[��]
All flags will be affected as per the accumulator contents.
SBI data; [�]←[�]−����−[��]
All flags will be affected as per the accumulator contents.
SBB M; �←�−�
????????????−[��]
All flags will be affected as per the accumulator contents.
SBI data; [�]←[�]−����−[��]
All flags will be affected as per the accumulator contents.
… Arithmetic Group of Instructions …
Increment Instructions
INR reg ;[���]←[���]+1
These instructions do not affect the CY flag but affect all other flags.
E.gif Z = 0, S = 1, and CY = 0 and contents of register is C = 1 1 1 1 1 1 1 1
then after the execution of the instruction INR C we have:
C = 0 0 0 0 0 0 0 0, Z = 1, S = 0, and CY = 0
INR M; �
��←�
��+�
All flags except carry flag will be affected after the execution of this instruction.
INX rp; [��]←[��]+1
No flag is affected with the execution of this instruction.
E.gif H = FF H, L = FF H, CY = 1, Z = 0
After the execution of the instruction INX H, we have the contents in H-L pair as: H = 25 H and L = 01 H ; the
contents of the flags will not be affected. So the carry and zero flag will have the same value as having before the
execution of this instruction i.e. CY = 1, Z = 0
Increment Instructions
INR reg ;[���]←[���]+1
These instructions do not affect the CY flag but affect all other flags.
E.gif Z = 0, S = 1, and CY = 0 and contents of register is C = 1 1 1 1 1 1 1 1
then after the execution of the instruction INR C we have:
C = 0 0 0 0 0 0 0 0, Z = 1, S = 0, and CY = 0
INR M; �
��←�
��+�
All flags except carry flag will be affected after the execution of this instruction.
INX rp; [��]←[��]+1
No flag is affected with the execution of this instruction.
E.gif H = FF H, L = FF H, CY = 1, Z = 0
After the execution of the instruction INX H, we have the contents in H-L pair as: H = 25 H and L = 01 H ; the
contents of the flags will not be affected. So the carry and zero flag will have the same value as having before the
execution of this instruction i.e. CY = 1, Z = 0
… Arithmetic Group of Instructions …
Decrement Instructions
DCR reg; [���]←[���]−1
These instructions do not affect the CY flag but affect all other flags.
E.gif Z = 0, S = 1, and CY = 0 and contents of D register is D = 0 0 0 0 0 0 0 0 ,
then after the execution of the instruction DCR D we have: C = 1 1 1 1 1 1 1 1, Z = 0, S = 1,
and CY = 0
DCR M ; �
��←�
��−�
all flags except carry flag will be affected after the execution of this instruction.
DCX rp; ��←��−1
No flag will be affected with the execution of this instruction.
For example if D = 23 H and E = 00 H
After the execution of DCX D, we have the contents in D-E pair as: D = 22 H and E = FF H
Decrement Instructions
DCR reg; [���]←[���]−1
These instructions do not affect the CY flag but affect all other flags.
E.gif Z = 0, S = 1, and CY = 0 and contents of D register is D = 0 0 0 0 0 0 0 0 ,
then after the execution of the instruction DCR D we have: C = 1 1 1 1 1 1 1 1, Z = 0, S = 1,
and CY = 0
DCR M ; �
��←�
��−�
all flags except carry flag will be affected after the execution of this instruction.
DCX rp; ��←��−1
No flag will be affected with the execution of this instruction.
For example if D = 23 H and E = 00 H
After the execution of DCX D, we have the contents in D-E pair as: D = 22 H and E = FF H
… Arithmetic Group of Instructions …
Rotate Instructions
In rotate instructions, the accumulator contents are shifted either left or right.
In some instructions shifting may be through CY flag or without CY flag.
RLC ; ??????
??????+�←??????
??????, ??????
�←??????
??????, �??????←??????
??????
In this instruction, the bits of the accumulator contents are shifted or rotated left.
The LSB of the accumulator is changed as MSB (before the execution).
The CY flag is modified as MSB (before the execution).
Only carry flag CY will be affected in this instruction
Rotate Instructions
In rotate instructions, the accumulator contents are shifted either left or right.
In some instructions shifting may be through CY flag or without CY flag.
RLC ; ??????
??????+�←??????
??????, ??????
�←??????
??????, �??????←??????
??????
In this instruction, the bits of the accumulator contents are shifted or rotated left.
The LSB of the accumulator is changed as MSB (before the execution).
The CY flag is modified as MSB (before the execution).
Only carry flag CY will be affected in this instruction
… Arithmetic Group of Instructions …
RAL
In this instruction, the bits of the accumulator contents will be shifted / rotated left through carry.
The content of carry flag CY will be stored in LSB of the accumulator and MSB of the accumulator will be stored
in CY flag. All other bits of the accumulator will be shifted to the left.
Only carry flag will be affected.
RAL
In this instruction, the bits of the accumulator contents will be shifted / rotated left through carry.
The content of carry flag CY will be stored in LSB of the accumulator and MSB of the accumulator will be stored
in CY flag. All other bits of the accumulator will be shifted to the left.
Only carry flag will be affected.
… Arithmetic Group of Instructions …
RRC RAR
RRC RAR
Logic Transfer Group …
Logical Instructions
ANA reg; [�]←[�].���.[���]
The ANA reginstruction clears (resets) the CY flag and all other flags are
modified according to the data conditions of the result.
Let A = 73H, C = C3 H, CY = 1 before the execution of the instruction ANA C.
Then after the instruction is executed we get:
A = 0 1 1 1 0 0 1 1 CY = 1
C = 1 1 0 0 0 0 1 1
A = 0 1 0 0 0 0 1 1 CY = 0
Logical Instructions
ANA reg; [�]←[�].���.[���]
The ANA reginstruction clears (resets) the CY flag and all other flags are
modified according to the data conditions of the result.
Let A = 73H, C = C3 H, CY = 1 before the execution of the instruction ANA C.
Then after the instruction is executed we get:
A = 0 1 1 1 0 0 1 1 CY = 1
C = 1 1 0 0 0 0 1 1
A = 0 1 0 0 0 0 1 1 CY = 0
… Logic Transfer Group …
ANA M; [�]←[�].���.[�
????????????]
E.g Let A = 19 H H = 25 H L = 00 H, M
2500= 37 H and CY = 1 before
the execution of the instruction ANA M.
Then after the instruction is executed we get:
A = 0 0 0 1 1 0 0 1 CY = 1
M
2500= 0 0 1 1 0 1 1 1
A = 0 0 0 1 0 0 0 1 CY = 0
ANI data; [�]←[�].���.����
ANA M; [�]←[�].���.[�
????????????]
E.g Let A = 19 H H = 25 H L = 00 H, M
2500= 37 H and CY = 1 before
the execution of the instruction ANA M.
Then after the instruction is executed we get:
A = 0 0 0 1 1 0 0 1 CY = 1
M
2500= 0 0 1 1 0 1 1 1
A = 0 0 0 1 0 0 0 1 CY = 0
ANI data; [�]←[�].���.����
… Logic Transfer Group …
ORA reg ; [�]←[�].��.[���]
The ORA reginstruction clears (resets) the CY flag and all other flags are modified according
to the data conditions of the result.
E.gLet A = 73 H, C = C3 H, CY = 1 before the execution of the instruction ORA B.
Then after the instruction is executed we get:
A = 0 1 1 1 0 0 1 1 CY = 1
B =11 0 000 11
A = 1 1 1 1 0 0 1 1 CY = 0
ORA M; [�]←[�].��.[�
????????????]
ORI data ; [�]←[�].��.����
ORA reg ; [�]←[�].��.[���]
The ORA reginstruction clears (resets) the CY flag and all other flags are modified according
to the data conditions of the result.
E.gLet A = 73 H, C = C3 H, CY = 1 before the execution of the instruction ORA B.
Then after the instruction is executed we get:
A = 0 1 1 1 0 0 1 1 CY = 1
B =11 0 000 11
A = 1 1 1 1 0 0 1 1 CY = 0
ORA M; [�]←[�].��.[�
????????????]
ORI data ; [�]←[�].��.����
… Logic Transfer Group …
XRA reg; [�]←[�].���.[���]
The XRA reginstruction clears (resets) the CY flag and all other flags are modified according
to the data conditions of the result.
Let A = 73 H, D = C3 H, CY = 1 before the execution of the instruction XRA D.
Then after the instruction is executed we get:
A = 0 1 1 1 0 0 1 1 CY = 1
D = 1 1 0 0 0 0 1 1
A = 1 0 1 1 0 0 0 0 CY = 0
XRA M; [�]←[�].���.[�
????????????]
XRI data ; [�]←[�].���.����
XRA reg; [�]←[�].���.[���]
The XRA reginstruction clears (resets) the CY flag and all other flags are modified according
to the data conditions of the result.
Let A = 73 H, D = C3 H, CY = 1 before the execution of the instruction XRA D.
Then after the instruction is executed we get:
A = 0 1 1 1 0 0 1 1 CY = 1
D = 1 1 0 0 0 0 1 1
A = 1 0 1 1 0 0 0 0 CY = 0
XRA M; [�]←[�].���.[�
????????????]
XRI data ; [�]←[�].���.����
… Logic Transfer Group …
CMA; [�]←[ҧ�]
The execution of this instruction inverts each bit of the accumulator contents and the result is saved in the
accumulator.
Basically it produces 1’s complement of the accumulator contents.
No flag is affected with this instruction.
For example, if A = 0B H before the execution of CMA instruction
then after the execution of this instruction we have: A = 1 1 1 1 0 1 0 0 (F4)
CMA; [�]←[ҧ�]
The execution of this instruction inverts each bit of the accumulator contents and the result is saved in the
accumulator.
Basically it produces 1’s complement of the accumulator contents.
No flag is affected with this instruction.
For example, if A = 0B H before the execution of CMA instruction
then after the execution of this instruction we have: A = 1 1 1 1 0 1 0 0 (F4)
… Logic Transfer Group …
Compare Instructions
CMP reg
The contents of the given register are compared with the accumulator contents.
In fact the contents of the register are subtracted from the contents of accumulator and the
accumulator contents remain unchanged.
The zero flag Z is set if [A] = [reg] otherwise reset and carry flag CY is set if [A]< [reg]
otherwise reset.
MVI B, 00 H
MVI A, 09 H
LOOP INR B
CMP B
JNZ LOOP
The value of B will increase by each go in the loop and each time it is compared with
accumulator contents. Till the contents of B register are not equal to the contents of
Accumulator, the computer will execute the instructions inside the loop. When the value of B
register becomes equal to 09 H, the zero flag will be set and it will allow coming out of the
loop to execute the next instructions.
Compare Instructions
CMP reg
The contents of the given register are compared with the accumulator contents.
In fact the contents of the register are subtracted from the contents of accumulator and the
accumulator contents remain unchanged.
The zero flag Z is set if [A] = [reg] otherwise reset and carry flag CY is set if [A]< [reg]
otherwise reset.
MVI B, 00 H
MVI A, 09 H
LOOP INR B
CMP B
JNZ LOOP
The value of B will increase by each go in the loop and each time it is compared with
accumulator contents. Till the contents of B register are not equal to the contents of
Accumulator, the computer will execute the instructions inside the loop. When the value of B
register becomes equal to 09 H, the zero flag will be set and it will allow coming out of the
loop to execute the next instructions.
… Logic Transfer Group …
CMP M
CPI data
Miscellaneous Logical Instructions
CMC; ��←��
STC; ��←1
CMP M
CPI data
Miscellaneous Logical Instructions
CMC; ��←��
STC; ��←1
Branch Group …
Unconditional Jump Instructions
JMP address ; [��]←[�����]
This is an unconditional jump instruction. With the execution of this instruction, the program jump to the address
(or label) specified with the instruction.
Thisis a three byte instruction and no flag is affected.
In fact during the execution of JMP address (label) instruction, the address of the label is copied in the program
counter; and whenever the program fetches the next instruction the program counter will send the address of this
given label.
Unconditional Jump Instructions
JMP address ; [��]←[�����]
This is an unconditional jump instruction. With the execution of this instruction, the program jump to the address
(or label) specified with the instruction.
Thisis a three byte instruction and no flag is affected.
In fact during the execution of JMP address (label) instruction, the address of the label is copied in the program
counter; and whenever the program fetches the next instruction the program counter will send the address of this
given label.
… Branch Group …
Conditional Jump Instructions
In conditional jump instructions the program jumps to the instructions specified by the address
(or label) if the given condition is fulfilled.
However, if the given condition is not satisfied, the program will not jump to the specified
address (or label) rather it will proceed to the normal sequence.
JNZ address (label)2 ; [��]←�����??????��=0
----
----
DCR C
JNZ NEXT
MOV A, M
NEXT STA 2500 H
HLT
JZ address (label) ;[��]←�����??????��=1
Conditional Jump Instructions
In conditional jump instructions the program jumps to the instructions specified by the address
(or label) if the given condition is fulfilled.
However, if the given condition is not satisfied, the program will not jump to the specified
address (or label) rather it will proceed to the normal sequence.
JNZ address (label)2 ; [��]←�����??????��=0
----
----
DCR C
JNZ NEXT
MOV A, M
NEXT STA 2500 H
HLT
JZ address (label) ;[��]←�����??????��=1
… Branch Group …
JNC address (label); [��]←�����,??????���=0
During the execution of this instruction, it will check up the Carry flag modified by the preceding instruction.
If there is no carry (CY = 0 or CY flag is reset), the program will jump to the instruction specified by the address
(or label) otherwise it will proceed to the next instruction of the normal sequence.
JC address (label) ; [��]←�����,??????���=1
JM address (label) ; [��]←�����,??????��=1
When this instruction is executed, the program will jump to the instruction specified by the address (label) if the
result of the preceding instruction is minus or sign flag is set (S = 1) otherwise it will proceed to the next
instruction of the normal sequence.
JP address (label) ; [��]←�����,??????��=0
JPO address (label) ;[��]←�����,??????��=0
If the parity is odd or parity flag is reset (P = 0) as a result of the preceding instruction, the program will jump to
the instruction specified by the address (label) otherwise next instruction of the normal sequence will be executed.
JPE address (label) ; [��]←�����,??????��=1
JNC address (label); [��]←�����,??????���=0
During the execution of this instruction, it will check up the Carry flag modified by the preceding instruction.
If there is no carry (CY = 0 or CY flag is reset), the program will jump to the instruction specified by the address
(or label) otherwise it will proceed to the next instruction of the normal sequence.
JC address (label) ; [��]←�����,??????���=1
JM address (label) ; [��]←�����,??????��=1
When this instruction is executed, the program will jump to the instruction specified by the address (label) if the
result of the preceding instruction is minus or sign flag is set (S = 1) otherwise it will proceed to the next
instruction of the normal sequence.
JP address (label) ; [��]←�����,??????��=0
JPO address (label) ;[��]←�����,??????��=0
If the parity is odd or parity flag is reset (P = 0) as a result of the preceding instruction, the program will jump to
the instruction specified by the address (label) otherwise next instruction of the normal sequence will be executed.
JPE address (label) ; [��]←�����,??????��=1
… Branch Group …
CALL Instructions
The call instructions allow calling the subroutine program.
The address of the subroutine program is specified with the CALL instruction.
During the execution of CALL instruction, the current contents of program counter are saved on the stack and the
address of subroutine (specified with the CALL instruction) is copied in the program counter.
CALL Instructions
The call instructions allow calling the subroutine program.
The address of the subroutine program is specified with the CALL instruction.
During the execution of CALL instruction, the current contents of program counter are saved on the stack and the
address of subroutine (specified with the CALL instruction) is copied in the program counter.
… Branch Group …
Unconditional Call Instructions
CALL address; [��−1]←[���],[��−2]←[���],[��]←�������
Unconditional Call Instructions
CALL address; [��−1]←[���],[��−2]←[���],[��]←�������
… Branch Group …
In this program LXI SP, 2500 H initializes the stack pointer (stack pointer is represented by 2500 H.) i.e. the area
or memory locations less than 2500 H will be used for stack purposes.
When the instruction CALL 2300 H is executed, the address of the program counter will be 2109 H. The address
of the program counter will be saved on the stack.
For this stack pointer will be decremented by 1 and the high byte of the program counter (21 H) will be saved on
to it; the stack pointer will further be decremented by 1 and lower byte of the program counter (09 H) will be
stored on to it.
The decremented of the stack pointer will be current position of the stack.
The address given with the CALL instruction i.e. 2300 H will be saved or copied in the program counter.
The subroutine program ends at the instruction RET
The RET instruction takes the computer back to the main program.
The return saved (or pushed) on to the stack will be popped back to the program counter.
In this program LXI SP, 2500 H initializes the stack pointer (stack pointer is represented by 2500 H.) i.e. the area
or memory locations less than 2500 H will be used for stack purposes.
When the instruction CALL 2300 H is executed, the address of the program counter will be 2109 H. The address
of the program counter will be saved on the stack.
For this stack pointer will be decremented by 1 and the high byte of the program counter (21 H) will be saved on
to it; the stack pointer will further be decremented by 1 and lower byte of the program counter (09 H) will be
stored on to it.
The decremented of the stack pointer will be current position of the stack.
The address given with the CALL instruction i.e. 2300 H will be saved or copied in the program counter.
The subroutine program ends at the instruction RET
The RET instruction takes the computer back to the main program.
The return saved (or pushed) on to the stack will be popped back to the program counter.
… Branch Group …
Conditional Call Instructions
CNZ address ; [��−1]←[���],[��−2]←[���],[��]←�������??????��=0
CZ address; [��−1]←[���],[��−2]←[���],[��]←�������??????��=1
CNC address ; [��−1]←[���],[��−2]←[���],[��]←�������??????���=0
CC address ; ��−1←���,��−2←���,��←�������??????���=0
CM address; [��−1]←[���],[��−2]←[���],[��]←�������??????��=1
CP address ; [��−1]←[���],[��−2]←[���],[��]←�������??????��=0
CPO address ; [��−1]←[���],[��−2]←[���],[��]←�������??????��=0
CPE address;[��−1]←[���],[��−2]←[���],[��]←�������??????��=1
Conditional Call Instructions
CNZ address ; [��−1]←[���],[��−2]←[���],[��]←�������??????��=0
CZ address; [��−1]←[���],[��−2]←[���],[��]←�������??????��=1
CNC address ; [��−1]←[���],[��−2]←[���],[��]←�������??????���=0
CC address ; ��−1←���,��−2←���,��←�������??????���=0
CM address; [��−1]←[���],[��−2]←[���],[��]←�������??????��=1
CP address ; [��−1]←[���],[��−2]←[���],[��]←�������??????��=0
CPO address ; [��−1]←[���],[��−2]←[���],[��]←�������??????��=0
CPE address;[��−1]←[���],[��−2]←[���],[��]←�������??????��=1
… Branch Group …
Return Instructions
RNZ; Return if no zero
RZ; Return if zero
RNC; Return if no carry
RC ; Return if carry
RM; Return if minus
RP; Return if positive
RPO; Return parity is odd
RPE; Return parity is even
All the above return instructions are one byte instructions.
If the specified condition is satisfied, it will return to the main program; otherwise the execution of the next
instruction in the subroutine will be carried out.
Further the return instruction will pop the return address to the program counter.
e.g RNC;[���]←[��],[���]←[��+1]??????���=0
Return Instructions
RNZ; Return if no zero
RZ; Return if zero
RNC; Return if no carry
RC ; Return if carry
RM; Return if minus
RP; Return if positive
RPO; Return parity is odd
RPE; Return parity is even
All the above return instructions are one byte instructions.
If the specified condition is satisfied, it will return to the main program; otherwise the execution of the next
instruction in the subroutine will be carried out.
Further the return instruction will pop the return address to the program counter.
e.g RNC;[���]←[��],[���]←[��+1]??????���=0
Stack and Input / Output Instructions
Stack is a portion of read/write memory, which is primarily used for saving return address and data.
The stack is initialized by the instruction given below:
LXI SP, address
Push Instructions
In the stack not only the return address of the main program during the execution of CALL address instruction is
pushed but also the contents of registers may also be pushed to stack.
PUSH rp
PSW is known as program status word; it represents the accumulator and the flag contents i.e. A F
PUSH PSW ; it pushes or saves the contents of accumulator (A) and F (flag) registers on the stack.
Following steps are carried out during the execution of PUSH rpinstructions.
1.��←��−1
2.[�
�??????−1]←��
??????
3.��←��−2
4.[�
�??????−2]←��
??????
Stack is a portion of read/write memory, which is primarily used for saving return address and data.
The stack is initialized by the instruction given below:
LXI SP, address
Push Instructions
In the stack not only the return address of the main program during the execution of CALL address instruction is
pushed but also the contents of registers may also be pushed to stack.
PUSH rp
PSW is known as program status word; it represents the accumulator and the flag contents i.e. A F
PUSH PSW ; it pushes or saves the contents of accumulator (A) and F (flag) registers on the stack.
Following steps are carried out during the execution of PUSH rpinstructions.
1.��←��−1
2.[�
�??????−1]←��
??????
3.��←��−2
4.[�
�??????−2]←��
??????
… Stack and Input / Output Instructions …
Pop Instructions
POP rp
To retrieve the contents of registers from the stack, following POP instructions
are used.
During the execution of POP instructions following steps are carried out.
1.��
??????←[�
�??????]
2.��←��+1
3.��
??????←�
�??????−1
4.��←��+2
Pop Instructions
POP rp
To retrieve the contents of registers from the stack, following POP instructions
are used.
During the execution of POP instructions following steps are carried out.
1.��
??????←[�
�??????]
2.��←��+1
3.��
??????←�
�??????−1
4.��←��+2
… Stack and Input / Output Instructions …
It should be remembered that when a subroutine is called, it should save the contents of any register being used in
the main program using PUSH instruction in the stack; and when it returns back to the main program from the
subroutine program the contents of the register should be retrieved from the stack using POP instruction as
discussed above.
The sequence of PUSH and POP instructions should be as:
PUSH PSW
PUSH D
PUSH B
PUSH H
----------
----------
POP H
POP B
POP D
POP PSW
It should be noted that POP retrieve the data from the stack just in reverse order of the data was PUSHedi.e. as
Last In First Out (LIFO) method is used in the stack.
It should be remembered that when a subroutine is called, it should save the contents of any register being used in
the main program using PUSH instruction in the stack; and when it returns back to the main program from the
subroutine program the contents of the register should be retrieved from the stack using POP instruction as
discussed above.
The sequence of PUSH and POP instructions should be as:
PUSH PSW
PUSH D
PUSH B
PUSH H
----------
----------
POP H
POP B
POP D
POP PSW
It should be noted that POP retrieve the data from the stack just in reverse order of the data was PUSHedi.e. as
Last In First Out (LIFO) method is used in the stack.
… Stack and Input / Output Instructions …
PUSH and POP instructions may also be used in the main program.
PUSH instruction is used before the CALL instruction and POP (in the reverse order) after the CALL instruction
in the main program as given below:
Main Program:
----------
----------
PUSH PSW
PUSH H
CALL LABEL
POP H
POP PSW
-----------
------------
In this program the contents of Accumulator, Flag, H and L registers are saved in the Stack before the execution of
CALL instruction.
After the execution of subroutine program the contents of the Accumulator, Flag, H and L registers are retrieved
and next instructions of the main program will be executed with restoration of earlier values of the registers.
PUSH and POP instructions may also be used in the main program.
PUSH instruction is used before the CALL instruction and POP (in the reverse order) after the CALL instruction
in the main program as given below:
Main Program:
----------
----------
PUSH PSW
PUSH H
CALL LABEL
POP H
POP PSW
-----------
------------
In this program the contents of Accumulator, Flag, H and L registers are saved in the Stack before the execution of
CALL instruction.
After the execution of subroutine program the contents of the Accumulator, Flag, H and L registers are retrieved
and next instructions of the main program will be executed with restoration of earlier values of the registers.
… Stack and Input / Output Instructions …
Further, the PUSH and POP instructions may be used in the subroutine program as given below.
This is generally done when the CALL instruction is used may times.
Main Program:
----------
----------
CALL LABEL
-----------
-----------
Subroutine Progam:
LABEL PUSH PSW
PUSH D
PUSH B
----------
----------
POP B
POP D
POP PSW
RET
Further, the PUSH and POP instructions may be used in the subroutine program as given below.
This is generally done when the CALL instruction is used may times.
Main Program:
----------
----------
CALL LABEL
-----------
-----------
Subroutine Progam:
LABEL PUSH PSW
PUSH D
PUSH B
----------
----------
POP B
POP D
POP PSW
RET
… Stack and Input / Output Instructions …
PCHL; [��]←[��]??????.�.[���]←[�]���[���]←[�]
No flag is affected with the instruction.
SPHL; [��]←[��]??????.�.[���]←[�]���[���]←[�]
None of the flags is affected with this instruction.
This is another way of initialization the stack pointer.
XTHL; �↔�
�??????, �↔�
�??????+�
No flag is affected with the instruction.
PCHL; [��]←[��]??????.�.[���]←[�]���[���]←[�]
No flag is affected with the instruction.
SPHL; [��]←[��]??????.�.[���]←[�]���[���]←[�]
None of the flags is affected with this instruction.
This is another way of initialization the stack pointer.
XTHL; �↔�
�??????, �↔�
�??????+�
No flag is affected with the instruction.
… Stack and Input / Output Instructions …
Input / Output Instructions
The input / output instructions deal with the input / output operations.
IN Port ; [�]←������������
It is two byte instruction and no flag is affected after the execution of this
instruction.
This instruction is basically used to read the data from the input devices such as
data read from keyboard, switches etc. during the computer run.
OUT Port ; ������←[�]
This two byte output instruction is used to send the contents of accumulator to the
specified port.
Input / Output Instructions
The input / output instructions deal with the input / output operations.
IN Port ; [�]←������������
It is two byte instruction and no flag is affected after the execution of this
instruction.
This instruction is basically used to read the data from the input devices such as
data read from keyboard, switches etc. during the computer run.
OUT Port ; ������←[�]
This two byte output instruction is used to send the contents of accumulator to the
specified port.
Instruction Cycles and Timing Diagram of 8085 ...
The sequence of operations that a processor has to carry out while executing the instruction is
called Instruction Cycle.
Each instruction cycle of a processor in turn consists of a number of machine cycles.
The machine cycles are the basic operations performed by the processor.
Toexecute an instruction, the processor executes one or more machine cycles in a particular
sequence.
The machine cycles of a processor are also called Processor Cycles.
The manufacturers of microprocessors define the timings and status of various signals during
the processor cycles.
In general,Instruction cycle = Fetch cycle + Execute cycle
The fetch cycle is executed to fetch the opcode from the memory and the execute cycle is
executed to decode the instruction and to perform the work specified by the instruction.
The sequence of operations that a processor has to carry out while executing the instruction is
called Instruction Cycle.
Each instruction cycle of a processor in turn consists of a number of machine cycles.
The machine cycles are the basic operations performed by the processor.
Toexecute an instruction, the processor executes one or more machine cycles in a particular
sequence.
The machine cycles of a processor are also called Processor Cycles.
The manufacturers of microprocessors define the timings and status of various signals during
the processor cycles.
In general,Instruction cycle = Fetch cycle + Execute cycle
The fetch cycle is executed to fetch the opcode from the memory and the execute cycle is
executed to decode the instruction and to perform the work specified by the instruction.
... Instruction Cycles and Timing Diagram of 8085 ...
The 8085 microprocessor has seven basic machine cycles. These are:
Opcodefetchcycle (4T or 6T)
Memory read cycle (3T)
Memory write cycle (3T)
IO read cycle (3T)
IO writecycle (3T)
Interrupt acknowledge cycle (6T or 12T)
Bus idlecycle (2T or 3T)
Each instruction of the 8085 processor consists of one to five machine cycles
The time taken by the processor to execute a machine cycle is expressed in T states.
One T-state is equal to the time period of the internal clock signal of the processor.
The T-state starts at the falling edge of a clock.
The 8085 microprocessor has seven basic machine cycles. These are:
Opcodefetchcycle (4T or 6T)
Memory read cycle (3T)
Memory write cycle (3T)
IO read cycle (3T)
IO writecycle (3T)
Interrupt acknowledge cycle (6T or 12T)
Bus idlecycle (2T or 3T)
Each instruction of the 8085 processor consists of one to five machine cycles
The time taken by the processor to execute a machine cycle is expressed in T states.
One T-state is equal to the time period of the internal clock signal of the processor.
The T-state starts at the falling edge of a clock.
... Instruction Cycles and Timing Diagram of 8085 ...
Timing diagram
The timing diagram provides information about the various conditions
(high state or low state or high impedance state) of the signals while a
machine cycle is executed.
The timing diagrams are supplied by the manufacturer of the
microprocessor.
The timing diagrams are essential for a system designer.
Only from the knowledge of the timing diagrams, the matched
peripheral devices like memories, ports, etc., can be selected to form a
system with a microprocessor as CPU.
Timing diagram
The timing diagram provides information about the various conditions
(high state or low state or high impedance state) of the signals while a
machine cycle is executed.
The timing diagrams are supplied by the manufacturer of the
microprocessor.
The timing diagrams are essential for a system designer.
Only from the knowledge of the timing diagrams, the matched
peripheral devices like memories, ports, etc., can be selected to form a
system with a microprocessor as CPU.
Opcode Fetch Machine Cycle …
Each instruction of the processor has an one byte
opcode.
The opcodes are stored in the memory.
The opcode fetch machine cycle is executed by
the processor to fetch the opcode from memory.
Hence, every instruction starts with an opcode
fetch machine cycle.
The time taken by the processor to execute the
opcode fetch cycle is either 4T or 6T.
In this time, the first 3T states are used for
fetching the opcode from the memory and the
remaining T states are used for internal
operations by the processor.
Each instruction of the processor has an one byte
opcode.
The opcodes are stored in the memory.
The opcode fetch machine cycle is executed by
the processor to fetch the opcode from memory.
Hence, every instruction starts with an opcode
fetch machine cycle.
The time taken by the processor to execute the
opcode fetch cycle is either 4T or 6T.
In this time, the first 3T states are used for
fetching the opcode from the memory and the
remaining T states are used for internal
operations by the processor.
…Opcode Fetch Machine Cycle
1.At the falling edge of the first T-state (T1), the microprocessor outputs the low byte address on
AD0-AD7 lines and high byte address on A8 to A15 lines.
ALE is asserted high to enable the external address latch.
The other control signals are asserted as follows: IO/M=0, S0 = 1, S1 = 1.
2.At the middle of T1, the ALE is asserted low and this enables the external address latch to take
low byte of the address and keep on its output lines.
3.In the second T-state (T2), the memory is requested for read by asserting read line low. When
read is asserted low, the memory is enabled for placing the opcode on the data bus. The time
allowed for memory to output the opcode is the time during which read remains low.
4.In the third T-state (T3), the read signal is asserted high. On the rising edge of the read signal,
the opcode is latched into the microprocessor. Other control signals remain in the same state
until the next machine cycle.
5.The fourth T-state (T4) is used by the processor for internal operations to decode the
instruction and encode it into various machine cycles, and also for completing the task
specified by the 1-byte instruction. During this state (T4), the address and the data bus will be
in high impedance state
1.At the falling edge of the first T-state (T1), the microprocessor outputs the low byte address on
AD0-AD7 lines and high byte address on A8 to A15 lines.
ALE is asserted high to enable the external address latch.
The other control signals are asserted as follows: IO/M=0, S0 = 1, S1 = 1.
2.At the middle of T1, the ALE is asserted low and this enables the external address latch to take
low byte of the address and keep on its output lines.
3.In the second T-state (T2), the memory is requested for read by asserting read line low. When
read is asserted low, the memory is enabled for placing the opcode on the data bus. The time
allowed for memory to output the opcode is the time during which read remains low.
4.In the third T-state (T3), the read signal is asserted high. On the rising edge of the read signal,
the opcode is latched into the microprocessor. Other control signals remain in the same state
until the next machine cycle.
5.The fourth T-state (T4) is used by the processor for internal operations to decode the
instruction and encode it into various machine cycles, and also for completing the task
specified by the 1-byte instruction. During this state (T4), the address and the data bus will be
in high impedance state
Memory Read Machine Cycle …
The memory read machine cycle is executed by the
processor to read a data byte from memory.
Theprocessor takes 3T states to execute this cycle.
1.At the falling edge of T1, the microprocessor outputs the
low byte address on AD0 -AD7 lines and high byte
address on A8 -A15 lines.
ALE is asserted high to enable the external address latch.
The other control signals are asserted as follows:
IO/M=0,S0 = 0, S1 = 1.
2.At the middle of T1, the ALE is asserted low and this
enables the external address latch to take low byte of
address and keep on its output lines.
The memory read machine cycle is executed by the
processor to read a data byte from memory.
Theprocessor takes 3T states to execute this cycle.
1.At the falling edge of T1, the microprocessor outputs the
low byte address on AD0 -AD7 lines and high byte
address on A8 -A15 lines.
ALE is asserted high to enable the external address latch.
The other control signals are asserted as follows:
IO/M=0,S0 = 0, S1 = 1.
2.At the middle of T1, the ALE is asserted low and this
enables the external address latch to take low byte of
address and keep on its output lines.
… Memory Read Machine Cycle
3.In the second T-state (T2), the memory is requested for read by asserting the read signal low.
When the read signal is asserted low, the memory is enabled for placing the data on the data
bus. The time allowed for memory to output the data is the time during which read remains
low.
4.At the end of T3, the read signal is asserted high. On the rising edge of the read signal, the
data is latched into the themicroprocessor. Other control signals remain in the same state until
the next machine cycle.
3.In the second T-state (T2), the memory is requested for read by asserting the read signal low.
When the read signal is asserted low, the memory is enabled for placing the data on the data
bus. The time allowed for memory to output the data is the time during which read remains
low.
4.At the end of T3, the read signal is asserted high. On the rising edge of the read signal, the
data is latched into the themicroprocessor. Other control signals remain in the same state until
the next machine cycle.
Memory Write Machine Cycle …
The memory write machine cycle is executed by the
processor to write a data byte in a memory location.
The processor takes 3T states to execute this machine
cycle. The timings of various signals during memory write
cycle are shown in Fig. 3.4.
1.1. At the falling edge of T1, the microprocessor outputs
the low byte address on AD0 -AD7 lines and high byte
address on A8 to A15 lines.
ALE is asserted high to enable the external address latch.
The other control signals are asserted as follows: IO/M=O, S0 =
1, S1 = 0.
2.At the middle of T1, the ALE is asserted low and this
enables the external address latch for latching the low byte
address into its output lines.
The memory write machine cycle is executed by the
processor to write a data byte in a memory location.
The processor takes 3T states to execute this machine
cycle. The timings of various signals during memory write
cycle are shown in Fig. 3.4.
1.1. At the falling edge of T1, the microprocessor outputs
the low byte address on AD0 -AD7 lines and high byte
address on A8 to A15 lines.
ALE is asserted high to enable the external address latch.
The other control signals are asserted as follows: IO/M=O, S0 =
1, S1 = 0.
2.At the middle of T1, the ALE is asserted low and this
enables the external address latch for latching the low byte
address into its output lines.
… Memory Write Machine Cycle
3.In the falling edge of T2, the processor outputs data on AD0 to AD7 lines and then, request
memory for write operation by asserting the write control signal WR to low.
4.At the end of T3, the processor asserts WR high. This enables the memory to latch the data
into it. The memory should prepare itself to accept the data within the time duration in which
the write control signal remains low. Other control signals remain in the same state until the
next machine cycle.
3.In the falling edge of T2, the processor outputs data on AD0 to AD7 lines and then, request
memory for write operation by asserting the write control signal WR to low.
4.At the end of T3, the processor asserts WR high. This enables the memory to latch the data
into it. The memory should prepare itself to accept the data within the time duration in which
the write control signal remains low. Other control signals remain in the same state until the
next machine cycle.
IO Read Cycle And IO Write Cycle
LXI rp, data
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