MISRA and Polyspace Guideline and Trap handlng.pptx

In this ppt one can learn about the MISRA and Polyspace guideline and also about the Trap system in infenion TC3xx microcontroller.

1. BRIEFING ON STATIC ANALYSIS,MISRA RULES OVERVIEW & POLYSPACE CODE STATIC ANALYSIS:- Method of program debugging that is done by examining the code without executing the program. The static analysis is done because, Bugs found during testing are 10 times more expensive than bugs found during development and this rate increases in the production phase. The key aspects of the static analysis, Identifies coding problems early in the development cycle. Ensure quality code and coding standard compliance. Reduces the risk of program failure. Static Analysis is done using tools like QAC, Polyspace , Klockworks , Parasoft , PC- Link.

2. MISRA GUIDELINE MISRA- Motor Industry Software Reliability Association . Made up of Manufactures, component suppliers, and engineering consultancies. Provides coding standard for developing safety- critical systems (both embedded control system and standalone software) They provide coding guidelines for the developers to achieve uniformity and standard in the software development. MISRA guidelines classification:- Advisory Guidelines Required Guidelines Mandatory Guidelines.

3. POLYSPACE Polyspace is  a static code analysis tool that helps engineers develop C, C++, and Ada embedded software that is safe, secure, and compliant with industry standards.   Polyspace comes with following products: Polyspace Bug Finder. Polyspace code prover Polyspace spooler Report gener ator Polyspace can verify C oding Rules Coding standards (MISRA) Code defects Run-time error Code metrics In the development process it helps in coding and review, Unit testing and integration testing, certification document.

4. TRICORETM TC1.6.2 CORE MICROCONTROLLER It is a 32 bit microcontroller used for real time application in automotive safety system. DSP architecture optimized for real-time embedded systems. The TriCore Instruction Set Architecture (ISA) combines the real-time capability of a microcontroller, the computational power of a DSP, and the high performance/price features of a RISC load/store architecture, in a compact re-programmable core.

5. FEATURES It is a 32 bit microcontroller. It has 32 General purpose register 15 are address register, 15 are data register, PSW, PC, PCXI. The architecture can access up to 4 GBytes (address width is 32-bits) of unified program and I/O memory. The architecture supports both 16-bit and 32-bit instruction formats.  reduce code space, lowering memory requirements, system and power consumption. Most instructions executed in one cycle. Optional Floating-Point Unit (FPU) and Memory Management Unit (MMU). Flexible interrupt prioritization scheme. It has a special routine for trap system called Trap service routine (TSR).

6. TRAP HANDLING IN INFINEON ARCHITECTURE Trap occurs due to the following results in the microcontroller Non-Maskable Interrupt(NMI) Instruction Exception Memory Management Exception Illegal access Traps are always active. There are 8 different classes of traps Each trap has its own trap handler accessed through the trap vector. Each trap class has a trap identification number[TIN]. When a trap occurs, a trap identifier is generated by hardware. The trap identifier has two components: • The Trap Class Number (TCN) used to index into the trap vector table. • The Trap Identification Number (TIN) which is loaded into the data register D[15] of 32 bytes.

7. TIN Name Synch. / Asynch . HW / SW HW /SW Definition Definition Class 0- Memory Management Unit Trap VAF Synch. HW HW Virtual Address Fill. Virtual Address Fill. 1 VAP Synch. HW HW Virtual Address Protection. Virtual Address Protection. Class 1 - Internal Protection traps 1 PRIV Synch. HW Privileged Instruction. 2 MPR Synch. HW Memory Protection Read. 3 MPW Synch. HW Memory Protection Write. 4 MPX Synch. HW Memory Protection Execution. 5 MPP Synch. HW Memory Protection Peripheral Access. 6 MPN Synch. HW Memory Protection Null Address. 7 GRWP Synch. HW Global Register Write Protection. Class 2 - Instruction Errors 1 IOPC Synch. HW Illegal Opcode. 2 UOPC Synch. HW Unimplemented Opcode. 3 OPD Synch. HW Invalid Operand specification. 4 ALN Synch. HW Data Address Alignment. 5 MEM Synch. HW Invalid Local Memory Address. Class 3 - Context Management 1 FCD Synch. HW Free Context List Depletion 2 CDO Synch. HW Call Depth Overflow. 3 CDU Synch. HW Call Depth Underflow. TRAP CLASSES

8. TIN Name Synch. / Asynch. HW / SW Definition 4 FCU Synch. HW Free Context List Underflow (FCX = 0). 5 CSU Synch. HW Call Stack Underflow (PCX = 0). 6 CTYP Synch. HW Context Type (PCXI.UL wrong). 7 NEST Synch. HW Nesting Error: RFE with non-zero call depth. Class 4 – System Bus and Peripheral errors 1 PSE Synch. HW Program Fetch Synchronous Error. 2 DSE Synch. HW Data Access Synchronous Error. 3 DAE Asynch. HW Data Access Asynchronous Error. 4 CAE Asynch HW Coprocessor Trap Asynchronous Error. 5 PIE Synch HW Program Memory Integrity Error. 6 DIE Asynch HW Data Memory Integrity Error. 7 TAE Asynch HW Temporal Asynchronous Error Class 5 – Assertion Traps 1 OVF Synch. SW Arithmetic Overflow. 2 SOVF Synch. SW Sticky Arithmetic Overflow. Class 6 – System Calls SYS Synch. SW System Call. Class 7 – Non- Maskable Interrupt NMI Asynch. HW Non-Maskable Interrupt. CONT.

9. SYNCHRONOUS TRAPS- Occurs due to, 1)Attempt to execute a specific instructions 2) Attempt to access a virtual address that requires the intervention of memory- management unit. ASYNCHRONOUS TRAPS:- Occurs due to, 1) Indirectly from instructions that have been previously executed, direct association with those instructions has been lost. 2)Non-Maskable Interrupt(NMI) Interrupts that can’t be ignored it is a time critical response. HARDWARE TRAPS:- Occurs due to, the attempted execution of a particular instruction 1) Illegal instruction traps 2)Memory protection traps 3)Data memory misalignment traps, comes under this. SOFTWARE TRAPS:- It occurs due to, Executing a System call syscall -program request a service from kernel. TRAP HANDLING:- It is different from interrupttraps doesn’t change the CPU interrupt priority, so the ICR.CCPN field is not updated.[ICR.CCPN-The interrupt control register holds the current CPU priority number.

10. WORKING OF TRAP HANDLING SYSTEM INITIAL SETUP:- The Upper context is saved  It refers to preserving the state of the processor or system before handling an exception or trap. It involves saving relevant registers, flags, and other context information. The return address in A[11] is updated. The TIN is loaded into D[15] The stack pointer in A[10] is set to the Interrupt Stack Pointer (ISP) when the processor was not previously using the interrupt stack (in case of PSW.IS = 0). The stack pointer bit is set for using the interrupt stack: PSW.IS = 1. The I/O mode is set to Supervisor mode: PSW.IO=10 B The current Protection Register Set is set to 0: PSW.PRS = 000B. The Call Depth Counter (CDC) is cleared, and the call depth limit is set for 64: PSW.CDC = 0000000B. Call Depth Counter is enabled, PSW.CDE = 1.

11. SETUP WHEN THE TRAP OCCURS, When the trap occurs  The hardware generates the TCN and the TIN. TCN- Trap Class Number TIN-Trap Identification Number. BTV [Base Trap Vector] register has the base address of the Trap vector table spaced with 32 bytes of trap handler or Trap service routine[TSR]. TCN is left shifted by 5 bit and ORd with BTV register which gives the address of the particular trap handler address for the respective trap. Respective Trap vector Registers are updated Base Trap Vector Table Pointer (BTV) Program Synchronous Error Trap Register (PSTR) Data Synchronous Error Trap Register (DSTR) Data Asynchronous Error Trap Register (DATR) Data Error Address Register (DEADD)

12. BASE TRAP VECTOR TABLE POINTER (BTV)

13. PROGRAM SYNCHRONOUS ERROR TRAP REGISTER (PSTR)

14. Data Synchronous Error Trap Register (DSTR)

15. Data Asynchronous Error Trap Register (DATR)

16. R EFERENCE: Infineon-AURIX_TC3xx_Part1-UserManual-v02_00-EN Infineon-AURIX_TC3xx_Architecture_vol1-UserManual-v01_00-EN Chrome-extension:// efaidnbmnnnibpcajpcglclefindmkaj /https://misra.org.uk/app/uploads/2021/06/MISRA-Compliance-2020.pdf. https://www.mathworks.com/videos/setting-up-polyspace-projects-99328.html