Modeling of Corner Effect in Multi-Gate MOSFET Devices.pptx

scaling of CMOS has caused many difficulties in the optimization of short-channel effects (SCEs) in conventional bulk silicon MOSFETs. Gate electrode’s control over channel is decreasing
as transistor’s gate length is scaled down, resulting in low electrostatic integrity of the device [1]. To resolve these issues, new device
architectures, e.g. multiple-gate MOSFET, and new materials, e.g.
high-k dielectrics and metal gate stacks, have been proposed. Multiple-gate MOSFETs have superior down-scaling characteristics
when compared to conventional MOSFETs due to excellent electrostatic integrity and FinFET is the most viable implementation of
multiple-gate structure due to its processing simplicity and compatibility with standard CMOS process [2]. Besides good SCE control, FinFET technology offers reduced device footprint for the
same transistor width when compared to standard bulk MOSFETs
and therefore more efficient use of silicon area [3]. FinFET is mainly
fabricated on silicon-on-insulator (SOI) wafers and has shown
excellent performance [4], whereas the body-tied or bulk FinFET
is made on standard bulk wafers and has attracted attention due
to its ability to be easily integrated with conventional CMOS [5].
Bulk FinFETs have several advantages compared to SOI FinFETs,
such as lower wafer cost, lower defect density, better heat removal
and better immunity to floating-body problem. It has been reported in [6] that bulk FinFET performance can be improved with
no increase in process cost or complexity.
A three-dimensional (3D) schematic view of FinFET is shown in
Fig. 1. Active area of the FinFET structure is a silicon wall between
the source and drain contacts. Technologically, silicon fin is carved
out in an etching process from the bulk silicon wafer in the case of
bulk FinFET and fin height (HFIN) determines transistor’s effective
channel width (WEFF). FinFET architecture can be double-gated or
triple-gated, depending on whether the hard-mask used for fin
etching is kept or removed [7]. In triple-gate FinFETs, the gate
wraps around the fin on all three sides, which results in effectively
wider transistors and therefore greater drive capabilities for the
same minimum feature size. Moreover, FinFETs offer improved
immunity to SCEs due to its multiple-gate architecture and thin
body. These characteristics imply FinFET’s potential for both
high-performance (HP) and low-standby power (LSP) applications
which are described in the ITRS roadmap [8]. Low-power mobile
multimedia (LPMM) technology is an emerging new family of
products, which requires speed in active mode (as HP) and low
power in standby mode (as LSP) [9]. Today, these applications
are covered by technologies at 0.18 lm node with supply voltage
of 1.8 V or even older CMOS generations. Therefore, there is a need
to perform feasibility studies of new device architectures not only
for the state-of-the-art technology nodes of 45 nm and less, but
also for nodes of 0.18 lm and above. Introd

1. Modeling of Corner Effect in Multi-Gate MOSFET Devices (- guided by Dr. Ria Bose) 1 MVD, MAKAUT (WB)

2. Name: Ritwik Datta Registration No.: 231000410413 Roll No.: 10013623001 Paper Name: Seminar – Term Paper Leading to Thesis Paper Code: PGMVD-293 To the examination for: Master of Technology (Microelectronics & VLSI Technology) Semester: Sem – II 2 MVD, MAKAUT (WB)

3. Outline Introduction Literature Survey Corner Effect Future Scope 3 MVD, MAKAUT (WB)

4. Introduction The scaling of MOSFET is approaching its limit due to SCEs. To overcome this problem multiple gate MOSFETs were introduced as a replacement of classical single gate MOSFET. Among the multiple gate structures, Gate all around structure offers superior control over the channel due to its surrounding gate structure, which in turn reduces SCEs effectively. Among the Gate all around structures, square gate all around MOSFET has higher current drive capability compared to cylindrical gate all around MOSFET. [ Santanu Sharma, Kabita Chaudhary , “A Novel Technique for Suppression of Corner Effect in Square Gate All Around Mosfet ”, Electrical and Electronic Engineering, 2(5): 336 – 341, 2012] Despite these advantages, square gate all around MOSFET exhibits a very undesirable characteristic known as corner effect which occurs due to the electrostatic coupling of two adjacent gates at the corners. Corner effect degrades the device performance by increasing the off state leakage current. The corner effect can be minimized by rounding the corner regions. 4 MVD, MAKAUT (WB)

5. Proposed Objective Study of impact of corner effect during sub-threshold. Modeling of current in sub-threshold considering the corner effect. 5 MVD, MAKAUT (WB)

6. Literature Survey Year Author’s Name Title Contribution Limitation 2012 Santanu Sharma, Kabita Chaudhary A Novel Technique for Suppression of Corner Effect in Square Gate All Around Mosfet A new structure of square gate all around MOSFET known as “ square gate all around MOSFET with gate underlap ” has been proposed. A new structure of square gate all around MOSFET known as “ square gate all around MOSFET with gate underlap ” has been modeled and simulated. This structure reduces the total current of the device. Although this structure reduces the total current driving capability of the device still it protects the device from unwanted corner effect. 6 MVD, MAKAUT (WB)

7. Literature Survey Year Author’s Name Title Contribution Limitation 2015 Moreno et al. A new explicit and analytical model for square Gate-All-Around MOSFETs with rounded corners A new square GAA MOSFET with rounded corners inversion charge distribution model has been developed analytically including QMEs . A state-of-the-art simulator that self-consistently solves the 2D Schrodinger and Poisson equations has been employed to validate the model for different device sizes, corner curvatures and operation regimes. The ICC was modeled in cylindrical surrounding gate as well as in bulk and double-gate MOSFETs. The modeling of cylindrical devices can be performed in one dimension if right coordinate system is chosen. Nevertheless, the ICC definition for square with rounded corners GAA MOSFETs is not straightforward. 7 MVD, MAKAUT (WB)

8. Literature Survey Year Author’s Name Title Contribution Limitation 2020 D. Mukherjee and B. V. R. Reddy Design and development of a novel MOSFET structure for reduction of reverse bias pn junction leakage current Constructional modification of MOSFET transistor (inserting insulator layer in between p and n region to eliminate p-n junction except channel area) to control p-n junction leakage current. TCAD simulation performed on a 20 nm NMOS. 52% reduction in substrate leakage current was noted. Transistor conducts current in channel area and this area was not insulated in proposed structure. So no restriction was in flow of current and no reduction in substrate leakage current was found. 8 MVD, MAKAUT (WB)

9. Square GAA MOSFET 9 MVD, MAKAUT (WB)

10. Corner Effect Square gate all around MOSFET is a type of multi-gate MOSFET where the gate wraps around the four sides of the silicon channel. A layer of silicon dioxide is wrapped around the silicon surface which acts as an insulator between silicon surface and gate electrode. At the corner regions of the device due to the electrostatic coupling of two adjacent gates, charge sharing effect occurs. This causes reduction of threshold voltage at the corners. The corners are turned on prior to the other parts of the device. Premature inversions occur at the corners ( corner effect ). 10 MVD, MAKAUT (WB)

11. The transistor doesn’t turn off exactly as V GS becomes lower than V th . Diffusion currents (non-negligible) make up a small channel between the source and drain. Diffusion current in subthreshold region, I S – specific current of the transistor, proportional to (W/L) ξ – non-ideality factor V T – thermal voltage, equal to ( kT /q) 11 MVD, MAKAUT (WB) I D = I S e ( Vԍѕ / ξVт )

12. Future Scope Devices can be made in which current loss due to corner effect will be reduced. Threshold voltage will remain constant all over the channel such that a same amount of current will flow through it. In case of rounded corner, the effect of charge sharing will be reduced. ICC ( Inversion Charge Centroid ) definition will be made easy for cylindrical surrounding gate as well as for bulk and double-gate MOSFETs. Inversion layer charges will increase by modeling Gate-to-channel capacitance. An unified model of drain current in multi-gate MOSFET under corner effect will lead scientists to a better possibility to improve the performances of advanced micro and nano -scale devices. 12 MVD, MAKAUT (WB)

13. THANK YOU 13 MVD, MAKAUT (WB)