MOSFET analysis VI characteristics and dc analysis

MOSFET analysis VI characteristics and dc analysis

1. MOSFET I-Vs

2. Substrate
Channel
Drain
Insulator
Gate
Operation of a transistor
V
SG > 0
n type operation
Positive gate bias attracts electrons into channel
Channel now becomes more conductive
More
electrons
Source
V
SD
V
SG

3. Some important equations in the
inversion regime (Depth direction)
V
T = 
ms + 2
B + 
ox
W
dm = [2
S(2
B)/qN
A]
Q
inv
= -C
ox
(V
G
- V
T
)

ox
= Q
s
/C
ox
Q
s
= qN
A
W
dm
V
T
= 
ms
+ 2
B
+ [4
S

B
qN
A
]/C
ox
Substrate
Channel
Drain
Insulator
Gate
Source
x

4. MOSFET Geometry
x
y
z
L
Z
S D
V
G
V
D

5. How to include y-dependent potential
without doing the whole problem over?

6. Assume potential V(y) varies slowly along
channel, so the x-dependent and y-dependent
electrostats are independent
(GRADUAL CHANNEL APPROXIMATION)
i.e.,
Ignore ∂E
x
/∂y
Potential is separable in
x and y

7. How to include y-dependent potentials?

S = 2
B + V(y)
V
G
= 
S
+ [2
S

S
qN
A
]/C
ox
Need V
G – V(y) > V
T to invert
channel at y (V increases
threshold)
Since V(y) largest at drain end, that
end reverts from inversion to
depletion first (Pinch off) 
SATURATION [V
DSAT = V
G – V
T]

8. j = qn
inv
v = (Q
inv
/t
inv
)v
I = jA = jZt
inv = ZQ
invv
So current:
Q
inv = -C
ox[V
G – V
T - V(y)]
v

= -
eff
dV(y)/dy

9. So current:
I = 
eff ZC
ox[V
G – V
T - V(y)]dV(y)/dy

I = 
eff ZC
ox[(V
G – V
T )V
D- V
D
2
/2]/L

Continuity implies ∫Idy = IL

10. But this current behaves like a parabola !!
I
D
V
D
I
D
sat
V
D
sat
I = 
eff
ZC
ox
[(V
G
– V
T
)V
D
- V
D
2
/2]/L

We have assumed inversion in our model (ie, always above pinch-off)
So we just extend the maximum current into saturation…
Easy to check that above current is maximum for V
Dsat = V
G - V
T
Substituting, I
Dsat
= (C
ox

eff
Z/2L)(V
G
-V
T
)
2

11. What’s Pinch off?
0
0 0
0
V
G V
G
Now add in the drain voltage to drive a current. Initially you get
an increasing current with increasing drain bias
0 V
D
V
G
V
G
When you reach V
Dsat = V
G – V
T, inversion is disabled at the drain
end (pinch-off), but the source end is still inverted

The charges still flow, just that you can’t draw more current
with higher drain bias, and the current saturates

12. Square law theory of MOSFETs
I = 
eff
ZC
ox
[(V
G
– V
T
)V
D
- V
D
2
/2]/L, V
D
< V
G
- V
T


I = 
eff
ZC
ox
(V
G
– V
T
)
2
/2L, V
D
> V
G
- V
T


J = qnv
n ~ C
ox
(V
G
– V
T
)
v ~ 
effV
D /L

NEW

13. Ideal Characteristics of n-channel
enhancement mode MOSFET

14. Drain current for REALLY small V
D
 
  
 
TGD
DTGinD
DDTGinD
VVV
VVVC
L
Z
I
VVVVC
L
Z
I











2
2
1
Linear operation
Channel Conductance:
)(
TGin
VD
D
D
VVC
L
Z
V
I
g
G




Transconductance:
Din
VG
D
m
VC
L
Z
V
I
g
D





15. In Saturation
•Channel Conductance:
•Transconductance:
 
2
2
TGinD VVC
L
Z
satI 
0



GVD
D
D
V
I
g
 
TGin
VG
D
m
VVC
L
Z
V
I
g
D





16. Equivalent Circuit – Low Frequency AC
•Gate looks like open circuit
•S-D output stage looks like current source with channel
conductance
gmdD
G
VG
D
D
VD
D
D
vgvgi
V
V
I
V
V
I
I
DG









17. •Input stage looks like capacitances gate-to-source(gate) and
gate-to-drain(overlap)
•Output capacitances ignored -drain-to-source capacitance
small
Equivalent Circuit – Higher Frequency AC

18. •Input circuit:
•Input capacitance is mainly gate capacitance
•Output circuit:
 
ggateggdgsin
vfCjvCCji  2
gmout
vgi
gate
m
in
out
fC
g
i
i


2
Din
VG
D
m
VC
L
Z
V
I
g
D




Equivalent Circuit – Higher Frequency AC

19. Maximum Frequency (not in saturation)
•C
i is capacitance per unit area and C
gate is total capacitance
of the gate
•F=f
max
when gain=1 (i
out
/i
in
=1)
2max
max
22
2
L
V
ZLC
CV
L
Z
f
C
g
f
Dn
i
iDn
gate
m








ZLCC
igate


20. Maximum Frequency (not in saturation)
2
max
2L
V
f
Dn




LVv
vL
D/
/
1
max




(Inverse transit time)
NEW

21. Switching Speed, Power Dissipation
t
on = C
oxZLV
D/I
ON
Trade-off: If C
ox too small, C
s and C
d take over and you lose
control of the channel potential (e.g. saturation)
(DRAIN-INDUCED BARRIER LOWERING/DIBL)
If C
ox
increases, you want to make sure you don’t control
immobile charges (parasitics) which do not contribute to
current.

22. Switching Speed, Power Dissipation
P
dyn = ½ C
oxZLV
D
2
f

P
st
= I
off
V
D

23. CMOS
NOT gate
(inverter)

24. CMOS
NOT gate
(inverter)
Positive gate turns nMOS on
V
in = 1 V
out = 0

25. CMOS
NOT gate
(inverter)
Negative gate turns pMOS on
V
in = 0 V
out = 1

26. So what?
• If we can create a NOT gate
we can create other gates
(e.g. NAND, EXOR)

27. So what?
Ring Oscillator

28. So what?
• More importantly, since one is open and one is shut at steady
state, no current except during turn-on/turn-off

 Low power dissipation

29. Getting the inverter output
Gain
ON
OFF

30. 0



G
VD
D
D
V
I
g
 
TGin
VG
D
m VVC
L
Z
V
I
g
D




What’s the gain here?

31. Signal Restoration

32. BJT vs MOSFET
• RTL logic vs CMOS logic
• DC Input impedance of MOSFET (at gate end) is infinite
Thus, current output can drive many inputs  FANOUT
• CMOS static dissipation is low!! ~ I
OFF
V
DD
• Normally BJTs have higher transconductance/current (faster!)
I
C = (qn
i
2
D
n/W
BN
D)exp(qV
BE/kT) I
D
= C
ox
W(V
G
-V
T
)
2
/L
g
m = I
C/V
BE = I
C/(kT/q) g
m = I
D/V
G = I
D/[(V
G-V
T)/2]
• Today’s MOSFET I
D
>> I
C
due to near ballistic operation
NEW

33. What if it isn’t ideal?
•If work function differences and oxide charges are present,
threshold voltage is shifted just like for MOS capacitor:
•If the substrate is biased wrt the Source (V
BS
) the
threshold voltage is also shifted
i
BAs
B
i
f
ms
i
BAs
BFBT
C
qN
C
Q
C
qN
VV
)2(2
2
)2(2
2










i
BSBAs
BFBT
C
VqN
VV
)2(2
2



34. Threshold Voltage Control
•Substrate Bias:
i
BSBAs
BFBT
C
VqN
VV
)2(2
2


 
BBSB
i
As
T
BSTBSTT
V
C
qN
V
VVVVV




22
2
)0()(

35. Threshold Voltage Control-substrate bias

36. It also affects the I-V
V
G
The threshold voltage is increased due to the depletion region
that grows at the drain end because the inversion layer shrinks
there and can’t screen it any more. (W
d > W
dm)
Q
inv = -C
ox[V
G-V
T(y)], I = -
effZQ
invdV(y)/dy
V
T(y) =  + √2
sqN
A/C
ox

 = 2
B + V(y)

37. It also affects the I-V
IL = ∫
eff
ZC
ox
[V
G
– (2
B
+V) - √2
s
qN
A
(2
B
+V)/C
ox
]dV
I = (Z
effC
ox/L)[(V
G–2
B)V
D –V
D
2
/2
-2√2
s
qN
A
{(2
B
+V
D
)
3/2
-(2
B
)
3/2
}/3C
ox
]

38. We can approximately include this…
Include an additional charge term from the
depletion layer capacitance controlling V(y)
Q = -C
ox[V
G-V
T]+(C
ox + C
d)V(y)
where C
d
= 
s
/W
dm
Q = -C
ox
[V
G
–V
T
- MV(y)], M = 1 + C
d
/C
ox
I
D = (Z
effC
ox/L)[(V
G-V
T - MV
D/2)V
D]

39. Comparison between different models
Square Law Theory
Body Coefficient
Bulk Charge Theory
Still not good below threshold or above saturation

40. Mobility
•Drain current model assumed constant mobility in channel
•Mobility of channel less than bulk – surface scattering
•Mobility depends on gate voltage – carriers in inversion
channel are attracted to gate – increased surface scattering
– reduced mobility

41. Mobility dependence on gate voltage
)(1
0
TGVV



42. Sub-Threshold Behavior
•For gate voltage less than the threshold – weak inversion
•Diffusion is dominant current mechanism (not drift)
L
Lnon
qAD
y
n
qADAJI
nnDD
)()(




kTVq
i
kTq
i
DBs
Bs
enLn
enn
/)(
/)(
)(
)0(





43. Sub-threshold
 
kTqkTqV
kT
in
D
sD
B
ee
L
enqAD
I
//
/
1



We can approximate 
s
with V
G
-V
T
below threshold since all
voltage drops across depletion region
 
 kTVVqkTqV
kT
in
D
TGD
B
ee
L
enqAD
I
//
/
1



•Sub-threshold current is exponential function of applied gate voltage
•Sub-threshold current gets larger for smaller gates (L)

44. Subthreshold Characteristic
 
GD
VI
S


log
1
Subthreshold Swing

45. Tunneling transistor
–Band filter like operation
J Appenzeller et al, PRL ‘04
Ghosh, Rakshit, Datta
(Nanoletters, 2004)
(S
conf
)
min
=2.3(k
B
T/e).(et
ox
/m)
Hodgkin and Huxley, J. Physiol. 116, 449 (1952a)
Subthreshold slope = (60/Z) mV/decade
Much of new research depends on reducing S !

46. Much of new research depends on reducing S !
• Increase ‘q’ by collective motion (e.g. relay)
Ghosh, Rakshit, Datta, NL ‘03
• Effectively reduce N through interactions
Salahuddin, Datta

• Negative capacitance
Salahuddin, Datta
• Non-thermionic switching (T-independent)
Appenzeller et al, PRL
• Nonequilibrium switching
Li, Ghosh, Stan
• Impact Ionization
Plummer

47. More complete model – sub-threshold to
saturation
•Must include diffusion and drift currents
•Still use gradual channel approximation
•Yields sub-threshold and saturation behavior for long
channel MOSFETS
•Exact Charge Model – numerical integration















Ds
B
V
p
p
V
D
ns
D
p
n
VF
e
LL
Z
I
0
0
0
,,

48. Exact Charge Model (Pao-Sah)
– Long Channel MOSFET
http://www.nsti.org/Nanotech2006/WCM2006/WCM2006-BJie.pdf