N well process

NEETI YADAV MTECH. ELECTRONICS AND COMMUNICATION ENGINEERING , PONDICHERRY UNIVERSITY

1. FABRICATION OF CMOS USING N-WELL PROCESS SUBMITTED TO PRESENTED BY Dr. K. ANUSUDHA NEETI YADAV Assistant professor, M. Tech (ECE)-1 st yr Dept. of electronics engineering Reg .No . 21304026 DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING PONDICHERRY UNIVERSITY

2. INTRODUCTION Making of CMOS Using N-well. Step1: first we choose a substrate as a base for fabrication. For N-well, a p-type silicon substrate is selected. The substrate is now exposed to UV rays the photoresist present under the exposed regions of mask gets polymerized. CMOS or complementary Metal oxide semiconductor is a combination of NMOS and PMOS transistors. NMOS is an N-type metal oxide semiconductor. The importance of CMOS in semiconductor technology is its low power dissipation and low operation currents.

3. The fabrication process involves twenty steps, which are as follows: STEP1: SUBSTRATE Primarily, start the process with a p-substrate. P-substrate

4. STEP2: OXIDATION The oxidation process is done by using high-purity oxygen and hydrogen, which are exposed in an oxidation furnace approximately at 1000 degree centigrade.

5. STEP3:PHOTORESIST A Light-sensitive polymer that softens whenever exposed to light is called as photoresist layer. It is formed.

6. STEP4:MASKING The photoresist is exposed to UV Rays through the N-Well mask

7. STEP5:PHOTORESIST REMOVAL A Part of the photoresist layer is removed by treating the wafer with the basic or acidic solution.

8. STEP6:REMOVAL OF SiO2 USING ACID ETCHING The SiO2 oxidation layer is removed through the open area made by the removal of photoresist using hydrofluoric acid.

9. STEP7:REMOVAL OF PHOTORESIST The entire photoresist layer is stripped off, as shown in the below figure.

10. STEP8: FORMATION OF THE N-WELL By using ion implantation or diffusion process N-Well is formed.

11. STEP9:REMOVAL OF SiO2 Using the hydrofluoric acid, the remaining SiO2 is removed.

12. STEP 10:DEPOSITION OF POLYSILICON Chemical vapor deposition (CVD) Process is used to deposit a very thin layer of gate oxide.

13. STEP11:REMOVING THE LAYER BARRING A SMALL AREA FOR THE GATES Except the two small regions required for forming the gates of NMOS and PMOS, The remaining layer is stripped off.

14. STEP12:OXIDATION PROCESS Next, an oxidation layer is formed on this layer with two small regions for the formation of the gate terminals of NMOS and PMOS.

15. STEP13:MASKING AND N-DIFFUSION By using the masking process small gaps are made for the purpose of N-diffusion.

16. The n-type (n+) dopants are diffused or ion implanted, and the three n+ are formed for the formation of the terminals of NMOS.

17. STEP14:OXIDE STRIPPING The remaining oxidation layer is stripped off.

18. STEP15:P-DIFFUSION Similar to the above N-diffusion process, the p-diffusion regions are diffused to from the terminals of the PMOS.

19. STEP16:THICK FIELD OXIDE A thick-field oxide is formed in all regions except the terminals of the PMOS and NMOS.

20. STEP17:REMOVAL OF EXCESS METAL Aluminum is sputtered on the whole Wafer and the excess metal is removed from the wafer layer

21. STEP18:ASSIGNING THE NAMES OF THE TERMINALS OF THE NMOS AND PMOS The terminal of the PMOS and NMOS are made from respective gaps.

22. ADVANTAGES N-Well CMOS are superior to p-well because of lower substrate bias effects on transistor threshold voltage Lower parasitic capacitances associated with source and drain region Latch-up problems can be considerable reduced by using a low resistivity epitaxial p-type substrate However n-well process degrades the performance of poorly performing p-type transistor

23. DISADVANTAGES No substrate diodes, inputs more difficult to protect. Device gains are lower, I/O structures must be larger. Density of contemporary digital processes is actually determined by number and density of metal interconnection layers. Sapphire and silicon on SiO2 substrates are considerably more expensive.

24. CONCLUSION The proponents of the n-well approach, most notably Intel and Matsushita, claim that the n-well process is the best approach to a COMS Process because of its compatibility with their existing NMOS Processes.