ngôn ngữ VHDL, môn Kĩ thuật số, đại học bách khoa

code VHDL

1. VHDL
-VHDL laø ngoân ngöõ moâ taû phaàn cöùng.
-VHDLvieát taét cuûa VHSIC (Very High Speed Integrated
Circuit) Hardware Description Language
-VHDL khoâng phaân bieät chöõ vieát hoa vaø chöõ thöôøng.
databus Databus DataBus DATABUS
-VHDL laø ngoân ngöõ “ñònh daïng töï do”.
if (a=b) then
if (a=b) then
if (a =
b) then
NguyenTrongLuat 1

2. Thuaät ngöõ COMPONENT:
-Laø khaùi nieäm trung taâm moâ taû phaàn cöùng baèng VHDL ñeå bieåu
dieãn caùc caáp thieát keá töø coång ñôn giaûn ñeán 1 heä thoáng phöùc taïp.
-Moâ taû component bao goàm ENTITY vaø ARCHITECTURE.
-Moät component coù theå söû duïng caùc component khaùc.
d0
d1 y
sel
mux2to1
a
b
z
nand2
NguyenTrongLuat 2

3. Maõ VHDL cô baûn
LIBRARY
khai baùo thö vieän
ENTITY
thöïc theå
ARCHITECTURE
kieán truùc
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4. Ví duï:Maõ VHDL moâ taû component NAND 2 ngoõ vaøo
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYnand_gateIS
PORT(
a : IN STD_LOGIC;
b: IN STD_LOGIC;
z: OUT STD_LOGIC);
ENDnand_gate;
ARCHITECTUREmodelOFnand_gateIS
BEGIN
z<= aNANDb;
ENDmodel;
a
b
z
NguyenTrongLuat 4

5. LIBRARY LIBRARYieee;
USEieee.std_logic_1164.all;
-LIBRARY: khai baùo thö vieän ieee
-USE: söû duïng caùc ñònh nghóa goùi (package) std_logic_1164
ENTITYnand_gateIS
PORT(
a: IN STD_LOGIC;
b: IN STD_LOGIC;
z: OUT STD_LOGIC);
ENDnand_gate;
ENTITY
-ENTITY: ñaët teân cho entity (nand_gate)
-PORT:khai baùo caùc chaân xuaát/nhaäp
* Teân port (portname):a, b, z
* Kieåu port (mode):IN, OUT
* Kieåu tín hieäu (type):STD_LOGIC
a
b
z
Moâ taû caùc tín hieäu xuaát/nhaäp cuûa khoái component
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6. * Caùc kieåu chaân PORT I/0
IN:döõ lieäu ñi vaøo entity qua port vaø coù theå ñöôïc ñoïc trong entity.
OUT:döõ lieäu xuaát ra ngoaøi entity qua chaân port.
Port OUT khoâng theå ñoïc veà laïi entity.
INOUT:laø port 2 chieàu, cho pheùp döõ lieäu ñi vaøo hoaëc ra.
BUFFER:töông töï port OUT, nhöng ñöôïc pheùp ñoïc laïi bôûi entity.
IN
IN
IN
OUT
BUFFER
OUT
INOUT
NguyenTrongLuat 6

7. ARCHITECTURE
ARCHITECTUREmodelOFnand_gateIS
BEGIN
z<=aNANDb;
ENDmodel;
-ARCHITECTURE: ñaët teân cho architecture (model)
Moâ taû thieát keá beân trong cuûa khoái, chæ roõ moái quan heä
giöõa caùc ngoõ vaøo vaø ngoõ ra.
-Coù 3 loaïi moâ taû architecture
* Moâ taû caáu truùc (Structural)
* Moâ taû luoàng döõ lieäu (Dataflow)
* Moâ taû haønh vi (Behavioral)
a
b
z
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8. ÑOÁI TÖÔÏNG DÖÕ LIEÄU (Data object)
* Tín hieäu (signal):bieåu dieãn cho caùc daây keát noái cuûa maïch.
Noù ñöôïc khai baùo trong phaàn PORTcuûa khai baùo entityhoaëc
trong phaàn ñaàu trong architecture (tröôùc BEGIN).
SIGNALsignal_name: signal_type;
* Bieán (Variable):ñöôïc khai baùo vaø söû duïng trong process.
Bieán khoâng phaûi laø tín hieäu logic thaät.
VARIABLEvariable_name: variable_type;
* Haèng soá (Constant):giöõ moät giaù trò khoâng ñöôïc thay ñoåi
CONSTANTconstant_name : constant_type;
SIGNAL a: std_logic;
VARIABLE b : std_logic;
CONSTANT max: integer;
Caùc ñoái töôïng döõ lieäu coù theå ñöôïc ñaët giaù trò ñaàu, khai baùo sau
phaàn khai baùo kieåu döõ lieäu _type:= value;
CONSTANT max: integer : = 25;
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9. -Leänh gaùn tín hieäu:signal_name<=expression;
a<= NOT b AND c;
variable_name:=expression;
y := NOT a;
-Leänh gaùn bieán:
-Bieán (Variable) laø cuïc boä trong process.
-Pheùp gaùn bieán (Variable) cho giaù trò töùc thôøi, pheùp gaùn
cuûa tín hieäu (signal) bò treã (delay)
-Tín hieäu (Signal) coù theå quan saùt daïng soùng (waveform),
nhöng bieán (Variable) thì khoâng.
* Söï khaùc nhau giöõa Tín hieäu (Signal) vaø Bieán (Variable)
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10. KIEÅU DÖÕ LIEÄU (Data type)
-Caùc kieåu döõ lieäu laø ñaëc tính cuûa signal, variable, …
-Coù theå taïo ra caùc kieåu döõ lieäu môùi baèng leänh TYPE hoaëc
SUBTYPE
-Caùc döõ lieäu cuøng kieåu môùi ñöôïc gaùn hoaëc keát noái vôùi nhau
* Kieåu BIT vaø BIT_VECTOR:
-BIT coù giaù trò ‘0’ vaø ‘1’.
-BIT_VECTOR laø daõy (array) cuûa BIT.
* Kieåu INTEGER
* Kieåu BOOLEAN:coù giaù trò TRUE vaø FALSE.
* Kieåu lieät keâ (ENUMERATION)do ngöôøi söû duïng ñònh nghóa.
* Kieåu CHARACTER
* . . .
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11. SIGNAL a: STD_LOGIC;
SIGNAL b: STD_LOGIC_VECTOR(7 DOWNTO 0);
a laø tín hieäu STD_LOGIC kieåu 1 bit
b,c laø tín hieäu STD_LOGIC kieåu bus coù 8 bit
* STD_LOGIC: Value Meaning
‘X’Forcing (Strong driven) Unknown
‘0’Forcing (Strong driven) 0
‘1’Forcing (Strong driven) 1
‘Z’High Impedance
‘W’Weak (Weakly driven) Unknown
‘L’
Weak (Weakly driven) 0.
Models a pull down.
‘H’
Weak (Weakly driven) 1.
Models a pull up.
‘-’Don't Care
‘U’Uninitialized
-Coù 9 giaù trò
-Höõu ích khi moâ phoûng
-Chæ coù 3 giaù trò ‘0’, ‘1’,
‘Z’ laø coù theå toång hôïp
SIGNAL c: STD_LOGIC_VECTOR(0 TO 7);
-Laø kieåu tín hieäu quyeát
ñònh (coù theå ñöôïc laùi baèng
2 ngoõ vaøo)
NguyenTrongLuat 11

12. SIGNALa: STD_LOGIC;
SIGNALb: STD_LOGIC_VECTOR(3 DOWNTO0);
SIGNALc: STD_LOGIC_VECTOR(0 TO3);
SIGNALd: STD_LOGIC_VECTOR(7 DOWNTO0);
SIGNALe: STD_LOGIC_VECTOR(15 DOWNTO0);
SIGNALf: STD_LOGIC_VECTOR(8 DOWNTO0);
a<= ’1’; --giaù trò gaùn ñaët giöõa 1 daáu nhaùy ñôn ‘ ’
a<= b(2); --a <= b(2),
b<= "0000”; --giaù trò gaùn ñaët giöõa 1 daáu nhaùy keùp “ ”
c<= B”0000”; --B laø kyù hieäu cô soá 2 (coù theå boû)
d<= ”0110_0111”; --bieåu dieãn töøng nhoùm 4 bit phaân caùch _
e<= X”AF67”; --X laø kyù hieäu cô soá 16 (Hex)
f<= O”723”; --O laø kyù hieäu cô soá 8 (Octal)
b<= c; --b(3) <= c(0), b(2) <= c(1),
--b(1) <= c(2), b(0) <= c(3)
d(7 downto 6)<= ”11”;
c(0 to 2)<=e(7 downto 5);
Pheùp gaùn tín hieäu kieåu STD_LOGIC
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13. SIGNALa: STD_LOGIC_VECTOR(3 DOWNTO0);
SIGNALb: STD_LOGIC_VECTOR(3 DOWNTO0);
SIGNALc, d, e: STD_LOGIC_VECTOR(7 DOWNTO0);
a<= ”0000”;
b<= ”1111”;
c<= a& b; --c= “00001111”
d<= ’0’ & ”0001111”; --d= “00001111”
e<= ’0’ & ’0’ & ’0’ & ’0’ & ’1’ & ’1’ &
’1’ & ’1’; --e= “00001111”
Gheùp noái chuoãi (Concatenation)
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14. PHEÙP TOAÙN (Operator)
* Pheùp toaùn Logic (Logical Operator):
NOT AND OR NAND NOR XOR XNOR
Söû duïng cho kieåu: bit, bit_vector, boolean, std_logic, std_logic_vector.
* Pheùp toaùn quan heä (Relationship Operator):
= /= < <= > >=
So saùnh 2 toaùn haïng cuøng kieåu vaø keát quaû traû veà kieåu boolean
* Pheùp toaùn dòch (Shift Operator):
SLL SRL SLA SRA ROL ROR
* Pheùp toaùn coäng (Adding Operator):+ -
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15. * Pheùp toaùn nhaân (Multiplying Operator):
* / MOD REM
* Pheùp toaùn daáu (Sign Operator):-+
* Pheùp toaùn khaùc (Operator): ** ABS
* Thöù töï öu tieân thöïc hieän caùc pheùp toaùn
** ABS NOT
* / MOD REM
+ - (Daáu)
+ -&
= /= < <= > >=
AND OR NAND NOR XOR XNOR
Caùc pheùp toaùn cuøng loaïi khoâng coù öu tieân, neáu caàn söû duïng ( )
NguyenTrongLuat 15

16. MOÂ TAÛ THIEÁT KEÁ (Design description)
MOÂ TAÛ THIEÁT KEÁ
(Design description)
CAÁU TRUÙC
(Structural)
LUOÀNG DÖÕ LIEÄU
(Dataflow)
HAØNH VI
(Behavioral)
NguyenTrongLuat 16

17. MOÂ TAÛ CAÁU TRUÙC (Structural description)
-Söû duïng caùc khoái component coù caáp thaáp hôn.
-Caùc khoái component naøy ñöôïc keát noái theo thöù baäc.
-Caùc component caáp thaáp ñöôïc khai baùo baèng leänh
COMPONENT, ñaët ôû phaàn ARCHITECTURE (tröôùc BEGIN).
-Ñeå keát noái component caáp thaáp, thöïc hieän leänh thay theá trò
soá component(component instantiation) PORT MAP.
COMPONENT and2
PORT(x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
x1
y
x2
* Keát hôïp vò trí (positional association)
* Keát hôïp theo teân (named association)
Coù 2 caùch:
NguyenTrongLuat 17

18. COMPONENT and2
PORT(x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP( x1=> a, x2=> b,
y=> c );
...
* Keát hôïp theo teân (named association)
COMPONENTcomponent_name
port declarations;
END COMPONENT;
...
Label:component_name PORT MAP(
port_name1=> sig_name1,
port_name2=> sig_name2 );
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19. COMPONENT and2
PORT(x1,x2:IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
BEGIN
user1: and2 PORT MAP( a, b, c);
...
* Keát hôïp vò trí (positional association)
COMPONENTcomponent_name
port declarations;
END COMPONENT;
...
Label:component_name PORT MAP(
sig_name1, sig_name2, ... );
NguyenTrongLuat 19

20. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYxor3IS
PORT( a, b, c: INSTD_LOGIC;
result: OUTSTD_LOGIC);
ENDxor3;
ARCHITECTUREstructuralOFxor3IS
SIGNALu1_out:STD_LOGIC;
COMPONENTxor2
PORT(i1, i2: INSTD_LOGIC;
y : OUTSTD_LOGIC );
END COMPONENT;
BEGIN
u1: xor2PORT MAP( i1 => a, i2 => b,
y => u1_out);
u2: xor2PORT MAP( i1 => u1_out, i2 => c,
y => result);
ENDstructural;
a
b
c
result
VD:Thieát keá XOR 3 ngoõ vaøo
u1_out
NguyenTrongLuat 20

21. MOÂ TAÛ LUOÀNG DÖÕ LIEÄU (Dataflow description)
-Moâ taû luoàng döõ lieäu di chuyeån töø ngoõ vaøo ñeán ngoõ ra.
-Söû duïng caùc phaùt bieåu ñoàng thôøi (Concurrent statement):
* Pheùp gaùn baèng pheùp toaùn
-Caùc phaùt bieåu naøy ñöôïc thöïc thi cuøng thôøi ñieåm, vì vaäy thöù
töï caùc phaùt bieåu laø nhö nhau
* Pheùp gaùn WHEN -ELSE
* Pheùp gaùn WITH –SELECT -WHEN
* Pheùp taïo GENERATE
NguyenTrongLuat 21

22. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYxor3IS
PORT( a, b, c: INSTD_LOGIC;
result: OUTSTD_LOGIC);
ENDxor3;
ARCHITECTUREdataflowOFxor3IS
SIGNALu1_out: STD_LOGIC;
BEGIN
u1_out<= aXORb;
Result<= u1_outXORc;
ENDdataflow;
Result<= u1_outXORc;
u1_out<= aXORb;
a
b
c
result
u1_out
Pheùp gaùn baèng pheùp toaùn (OPERATOR)
NguyenTrongLuat 22

23. Pheùp gaùn tín hieäu theo ñieàu kieän (Condition Signal Assigment)
WHEN -ELSE
signal_name<= value1 WHENcondition1 ELSE
{value2 WHENcondition2 ELSE}
valueN ;
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYmux2to1IS
PORT( d0, d1 : INSTD_LOGIC;
sel: IN STD_LOGIC;
y: OUTSTD_LOGIC);
ENDmux2to1;
ARCHITECTUREdataflow1 OFmux2to1 IS
BEGIN
y<= d0WHENsel= ’0’ ELSEd1;
ENDdataflow1;
d0
d1 y
sel
mux2to1
sely
0
1
d0
d1
y<= d0WHENsel= ’0’ ELSE
d1 WHEN OTHERS;
VD:Mux2to1
NguyenTrongLuat 23

24. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYxnor2IS
PORT( a, b : INSTD_LOGIC;
c: OUTSTD_LOGIC);
ENDxnor2;
ARCHITECTUREdataflow1 OFxnor2 IS
BEGIN
c<= ’1’ WHENa= ’0’ AND b= ’0’ ELSE
’0’ WHENa= ’0’ AND b= ’1’ ELSE
’0’ WHENa= ’1’ AND b= ’0’ ELSE
’1’ WHENa= ’1’ AND b= ’1’ ELSE
’0’WHENOTHERS;
ENDdataflow1;
xnor2
a bc
0 0
0 1
1 0
1 1
1
0
0
1
VD:xnor2
a
b
c
NguyenTrongLuat 24

25. Pheùp gaùn tín hieäu coù choïn loïc (Select Signal Assigment)
WITH –SELECT -WHEN
WITHselect_signalSELECT
signal_name<= value1 WHENconst1_of_select_signal,
{value2 WHENconst2_of_select_signal,}
valueN WHEN OTHERS;
d0
d1 y
sel
mux2to1
sely
0
1
d0
d1
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYmux2to1IS
PORT( d0, d1 : INSTD_LOGIC;
sel: IN STD_LOGIC;
y: OUTSTD_LOGIC);
ENDmux2to1;
ARCHITECTUREdataflow2 OFmux2to1 IS
BEGIN
WITHselSELECT
y<= d0WHEN’0’,
d1 WHEN OTHERS;
ENDdataflow2;
NguyenTrongLuat 25

26. WITHselect_signal SELECT
signal_name<= value1 WHENconst1_of_select_signal,
{value2 WHENconst2_of_select_signal,}
valueN WHEN OTHERS;
Tham soá const_of_select_signal coù theå bieåu dieãn
nhieàu giaù trò rieâng bieät hoaëc 1 daõi giaù trò lieân tieáp.
PORT( d0, d1, d2, d3 : INSTD_LOGIC;
sel: IN STD_LOGIC_VECTOR(2 DOWNTO 0);
y: OUTSTD_LOGIC );
...
...
WITH selSELECT
y<= d0WHEN”001”,
d1WHEN”011” to ”101”,
d2WHEN”000” | ”111”,
d3 WHEN OTHERS;
NguyenTrongLuat 26

27. xnor2
a bc
0 0
0 1
1 0
1 1
1
0
0
1
VD:xnor2
a
b
c
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYxnor2IS
PORT( a, b : INSTD_LOGIC;
c: OUTSTD_LOGIC);
ENDxnor2;
ARCHITECTUREdataflow2 OFxnor2 IS
SIGNAL ab:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
ab<= a& b;
WITHabSELECT
c<= ’1’ WHEN”00” | ”11”,
’0’WHEN OTHERS;
ENDdataflow2;
NguyenTrongLuat 27

28. Phaùt bieåu FOR -GENERATE
GENERATE laø caùch ñeå taïo ra nhieàu tình huoáng (instance) cho
caùc phaùt bieåu ñoàng thôøi, thöôøng duøng cho caùc pheùp gaùn thay
theá trò soá töông ñöông component (component instantitation).
[Name:]FORindex_variable IN range GENERATE
concurent_statements;
END GENERATE[name];
g0:FORiIN0 to 3 GENERATE
z(i)<= x(i)and y(i+8);
END GENERATE;
xor_array: FORiIN7 downto 0 GENERATE
user: xor2 PORT MAP(
x(i), y(i), z(i) );
END GENERATE;
NguyenTrongLuat 28

29. GENERIC
-Laø caáu truùc ñeå ñöa 1 haèng soá vaøo trong entitygioáng khai baùo
CONSTANT.
-Tieän lôïi cuûa generic laø coù theå söû duïng noù trong pheùp gaùn
thay theá trò soá töông ñöông component (component
instantitation), ñeå söû duïng caùc giaù trò haèng soá khaùc nhau khi
tham chieáu component.
ENTITYentity_name IS
GENERIC(
generic_name1: data_type := default_values;
generic_name2: data_type := default_values;
)
PORT(
port_name: mode data_type;
... )
ENDentity_name;
NguyenTrongLuat 29

30. * Pheùp gaùn thay theá trò soá component coù GENERIC
Label:component_name
GENERIC MAP(
generic_name1=> sig_name1,
gereric_name2=> sig_name2);
PORT MAP(
port_name=> sig_name);
* Khai baùo component coù GENERIC
COMPONENTcomponent_name
GENERIC(
generic_name1: data_type := default_values;
...)
PORT(
port_name: mode data_type;
...)
ENDCOMPONENT;
NguyenTrongLuat 30

31. MOÂ TAÛ HAØNH VI ( Behavioral description)
-Moâ taû söï ñaùp öùng cuûa ngoõ ra theo ngoõ vaøo.
-Caùc phaùt bieåu tuaàn töï (Sequential statement): cho pheùp moâ taû
hoaït ñoäng tuaàn töï cuûa caùc tín hieäu
* Phaùt bieåu IF
* Phaùt bieåu CASE
* Phaùt bieåu LOOP
-Söû duïng phaùt bieåu PROCESSchöùa caùc leänh ñöôïc thöïc thi
tuaàn töï, phuï thuoäc vaøo thöù töï cuûa noù
NguyenTrongLuat 31

32. PROCESS
-Process thöïc hieän caùc leänh beân trong noù 1 caùch tuaàn töï.
Vì vaäy thöù töï cuûa caùc leänh raát quan troïng.
-Moät Architecture coù nhieàu Process. Caùc Process laø caùc phaùt
bieåu ñoàng thôøi
-Process ñöôïc kích hoaït khi coù söï thay ñoåi cuûa 1 tín hieäu.
[Name:]PROCESS(sensitivity list)
variable declarations
BEGIN
sequential statements
END PROCESS[Name];
Sensitivity list: danh saùch caûm nhaän
Variable declarations: khai baùo bieán
NguyenTrongLuat 32

33. * Danh saùch caûm nhaän (sensitivity list):
-Khai baùo caùc tín hieäu duøng ñeå kích hoaït Processkhi tín hieäu
thay ñoåi (thöôøng goïi laø söï kieän event). Thöôøng laø caùc tín hieäu
ngoõ vaøo.
-Khi Processñöôïc kích hoaït thì caùc phaùt bieåu beân trong
process ñöôïc thöïc hieän tuaàn töï. Khi thöïc hieän xong phaùt bieåu
cuoái cuøng thì Processvaøo traïng thaùi chôø (suspend).
* Khai baùo bieán (variable declaration):
Khai baùo caùc bieán cuïc boä söû duïng trong Process
* Phaùt bieåu tuaàn töï :
-Ñaët giöõa BEGIN vaø END cuûa Process.
-Goàm caùc pheùp gaùn tín hieäu vaø bieán, caùc phaùt bieåu tuaàn töï
IF, CASE, LOOP…
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34. Phaùt bieåu IF -THEN -ELSE
IFcondition1 THEN sequential_statements_1;
{ELSIFcondition2 THENsequential_statements_1 ;}
{ELSEsequential_statements_1; }
END IF;
d0
d1 y
sel
mux2to1
sely
0
1
d0
d1
VD:Mux2to1
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYmux2to1IS
PORT( d0, d1 ,sel : INSTD_LOGIC;
y: OUTSTD_LOGIC);
ENDmux2to1;
ARCHITECTUREbehavior1 OFmux2to1 IS
BEGIN
PROCESS (d0,d1,sel)
BEGIN
IFsel =’0’ THEN y<= d0;
ELSE y<= d1 ;
END IF;
END PROCESS;
ENDbehavior1;
NguyenTrongLuat 34

35. Phaùt bieåu CASE -WHEN
CASEselect_signal IS
WHENvalue1 => sequential_statements_1 ;
WHENvalue2 => sequential_statements_2 ;
WHEN OTHERS=> sequential_statements_N;
END CASE;
d0
d1 y
sel
mux2to1
sely
0
1
d0
d1
VD:Mux2to1
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYmux2to1IS
PORT( d0, d1 ,sel : INSTD_LOGIC;
y: OUTSTD_LOGIC);
ENDmux2to1;
ARCHITECTUREbehavior2 OFmux2to1 IS
BEGIN
PROCESS (d0,d1,sel)
BEGIN
CASEsel IS
WHEN ’0’ =>y<= d0;
WHEN OTHERS => y<= d1 ;
END CASE;
END PROCESS;
ENDbehavior2;
NguyenTrongLuat 35

36. Phaùt bieåu FOR -LOOP
[Name:]FORvariable_name IN range LOOP
sequential_statements;
END LOOP[name];
sqr:FOR iIN1 to 10 LOOP
a(i) := i*i;
END LOOP sqr;
FORjIN3 downto 0 LOOP
IFreset(j)= ’1’ THEN data(j) := ’0’;
END IF;
END LOOP;
Töông töï nhö phaùt bieåu ñoàng thôøi FOR_GENERATE.
NguyenTrongLuat 36

37. Phaùt bieåu WHILE -LOOP
i:=0;
WHILE(i<10) LOOP
s<= i;
i:= i+1;
END LOOP;
[Name:]WHILEcondition LOOP
sequential_statements;
END LOOP[name];
NguyenTrongLuat 37

38. THIEÁT KEÁ HEÄ TOÅ HÔÏP BAÈNG VHDL
-Heä toå hôïp coù theå ñöôïc thöïc hieän baèng caùc phaùt bieåu ñoàng
thôøi (concurent statement) vaø tuaàn töï (sequential statement).
-Phaùt bieåu ñoàng thôøi (concurent staement) ñöôïc duøng trong
moâ taû caáu truùc (structural description) vaø luoàng döõ lieäu
(dataflow description)
-Phaùt bieåu tuaàn töï (sequent statement) ñöôïc duøng trong moâ taû
haønh vi (dataflow description)
NguyenTrongLuat 38

39. BOÄ COÄNG
A
D
D
E
R
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYfulladderIS
PORT( x , y ,z : INSTD_LOGIC;
s, c: OUTSTD_LOGIC);
ENDfulladder;
ARCHITECTUREFunction OFfulladder IS
BEGIN
s<= x XORy XORz;
C<= (xAND y) OR (yAND z) OR (xAND z);
ENDFunction;
fulladder
x
y
s
z
c
NguyenTrongLuat 39
s = x y z
c = x y + y z + x z

40. adder4
a3
Cout
Cin
a2
a1
a0
b3
b2
b1
b0
s3
s2
s1
s0
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYadder4IS
PORT( Cin : INSTD_LOGIC;
a, b: IN STD_LOGIC_VECTOR(3 downto 0);
s: OUT STD_LOGIC_VECTOR(3 downto 0);
Cout: OUTSTD_LOGIC);
ENDadder4;
ARCHITECTUREStructure OFadder4 IS
SIGNALc: STD_LOGIC_VECTOR(1 to 3);
COMPONENT fulladder
PORT( x , y ,z : INSTD_LOGIC;
s, c: OUTSTD_LOGIC);
ENDCOMPONENT;
BEGIN
stage0: fulladder PORT MAP(a(0),b(0),Cin,s(0),c(1)) ;
stage1: fulladder PORT MAP(a(1),b(1),c(1),s(1),c(2)) ;
stage2: fulladder PORT MAP(a(2),b(2),c(2),s(2),c(3)) ;
stage3: fulladder PORT MAP(a(3),b(3),c(3),s(3),Cout) ;
ENDStructure;
Thieát keá boä coäng 4 bit adder4söû duïng fulladder
NguyenTrongLuat 40

41. LeänhUSEieee.std_logic_signed.all cho pheùp söû duïng
goùi (package) std_logic_signed,ñeå thöïc hieän pheùp toaùn soá
hoïc treân caùc tín hieäu std_logic.
Boä coäng 4 bit adder4söû duïng pheùp coäng soá hoïc
LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_signed.all;
ENTITYadder4IS
PORT( Cin : INSTD_LOGIC;
a, b: IN STD_LOGIC_VECTOR(3 downto 0);
s: OUT STD_LOGIC_VECTOR(3 downto 0);
Cout: OUTSTD_LOGIC);
ENDadder4;
ARCHITECTUREArithmetic OFfulladder IS
SIGNALsum: STD_LOGIC_VECTOR(4 downto 0);
BEGIN
sum <=(’0’& a ) + b+ Cin;
s <=sum(3 downto 0) ;
Cout <=sum(4);
ENDArithmetic;
NguyenTrongLuat 41

42. BOÄ DOÀN KEÂNH
M
U
X
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYmux4IS
PORT(
d0 , d1 ,d2 ,d3 : INSTD_LOGIC;
s: INSTD_LOGIC_VECTOR(1 downto 0);
y: OUTSTD_LOGIC);
ENDmux4;
ARCHITECTUREFunction OFmux4 IS
BEGIN
y<= (NOT s(1)AND NOT s(0)AND d0) OR
(NOT s(1)AND s(0)AND d1) OR
(s(1)AND NOT s(0)AND d2) OR
(s(1)AND s(0)AND d3 );
ENDFunction;
MUX4
d0
d1
d2
d3
s1
s0
y
s1 s0 y
0 0
0 1
1 0
1 1
d0
d1
d2
d3
NguyenTrongLuat 42
ARCHITECTUREDataflow OFmux4 IS
BEGIN
y<= d0 WHENs = ”00” ELSE
d1 WHENs = ”01” ELSE
d2 WHENs = ”10” ELSE
d3 WHENOTHERS;
ENDDataflow;
WITH sSELECT
y<= d0 WHEN”00”,
d1 WHEN”01”,
d2 WHEN”10”,
d3 WHENOTHERS;

43. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYmux16IS
PORT(
d: INSTD_LOGIC_VECTOR(15 downto 0);
c: INSTD_LOGIC_VECTOR(3 downto 0);
f: OUTSTD_LOGIC);
ENDmux16;
ARCHITECTUREStructure OFmux16IS
SIGNAL w:STD_LOGIC_VECTOR(0 to 3);
COMPONENTmux4
PORT(
d0 , d1 ,d2 ,d3 : INSTD_LOGIC;
s: INSTD_LOGIC_VECTOR(1 downto 0);
y: OUTSTD_LOGIC);
END COMPONENT;
BEGIN
M0: mux4 PORT MAP(d(0),d(1),d(2),d(3),c(1 downto 0),w(0));
M1: mux4 PORTMAP(d(4),d(5),d(6),d(7),c(1 downto 0),w(1));
M2: mux4 PORT MAP(d(8),d(9),d(10),d(11),c(1 downto 0),w(2));
M3: mux4 PORTMAP(d(12),d(13),d(14),d(15),c(1 downto 0),w(3));
M4: mux4 PORTMAP(w(0),w(1),w(2),w(3),c(3 downto 2),f);
END Structure;
NguyenTrongLuat 43
c3 c2 c1 c0f
0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1
d0
d1
d2
d3
d4
d5
d6
d7
d8
d9
d10
d11
d12
d13
d14
d15
Thieát keá MUX 16 →1söû duïng MUX 4 →1
mux16

44. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYmux16IS
PORT(
d: INSTD_LOGIC_VECTOR(15 downto 0);
c: INSTD_LOGIC_VECTOR(3 downto 0);
f: OUTSTD_LOGIC);
ENDmux16;
ARCHITECTUREStructure2 OFmux16IS
SIGNAL w:STD_LOGIC_VECTOR(0 to 3);
COMPONENTmux4
PORT(
d0 , d1 ,d2 ,d3 : INSTD_LOGIC;
s: INSTD_LOGIC_VECTOR(1 downto 0);
y: OUTSTD_LOGIC);
END COMPONENT;
BEGIN
G0: FORiIN0 to 3 GENERATE
MUXES: mux4 PORT MAP(
d(4*i),d(4*i+1),d(4*i+2),d(4*i+3),c(1 downto 0),w(i));
ENDGENERATE;
M4: mux4 PORTMAP(w(0),w(1),w(2),w(3),c(3 downto 2),f);
END Structure2;
NguyenTrongLuat 44
Söû duïng
GENERATE

45. BOÄ GIAÛI MAÕ
D
E
C
O
D
E
R
en x1 x0y3 y2 y1 y0
0 X X
1 0 0
1 0 1
1 1 0
1 1 1
0 0 0 0
0 0 0 1
0 0 1 0
0 1 0 0
1 0 0 0
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYdec2x4IS
PORT( en : INSTD_LOGIC;
x: INSTD_LOGIC_VECTOR(1 downto 0);
y: OUTSTD_LOGIC_VECTOR(3 downto 0));
ENDdec2x4;
ARCHITECTUREflow OFdec2x4 IS
SIGNAL
temp: STD_LOGIC_VECTOR(3 downto 0);
BEGIN
WITH x SELECT
temp <=”0001”WHEN”00” ,
”0010”WHEN”01” ,
”0100”WHEN”10” ,
”1000”WHEN”11” ,
”0000”WHEN OTHERS;
y<= tempWHENen= ’1’
ELSE”0000”;
ENDflow;
NguyenTrongLuat 45
y0
y1
y2
y3
x0
x1
en
dec2x4
ARCHITECTUREflow2 OF
dec2x4 IS
SIGNAL
en_x: STD_LOGIC_VECTOR(
2 downto 0);
BEGIN
en_x <=en & x;
WITH en_x SELECT
f <=”0001”WHEN”100” ,
”0010”WHEN”101” ,
”0100”WHEN”110” ,
”1000”WHEN”111” ,
”0000”WHEN OTHERS;
ENDflow2;

46. Thieát keá IC DECCODER 74138
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYdec138IS
PORT( c,b,a: INSTD_LOGIC;
g1,g2a,g2b: INSTD_LOGIC;
y: OUTSTD_LOGIC_VECTOR(7 downto 0));
ENDdec138;
ARCHITECTUREflow OFdec138 IS
SIGNAL
data: STD_LOGIC_VECTOR(2 downto 0);
temp: STD_LOGIC_VECTOR(7 downto 0);
BEGIN
data <=c &b &a;
WITH data SELECTtemp <=”11111110”WHEN”000” ,
”11111101”WHEN”001” ,
”11111011”WHEN”010” ,
”11110111”WHEN”011” ,
”11101111”WHEN”100” ,
”11011111”WHEN”101” ,
”10111111”WHEN”110” ,
”01111111”WHEN”111” ,
”11111111”WHEN OTHERS;
y<= tempWHEN(g1 ANDNOTg2a AND NOT g2b) = ’1’
ELSE”11111111”;
ENDflow;
NguyenTrongLuat 46

47. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYdec3to8IS
PORT(x: INSTD_LOGIC_VECTOR(2 downto 0);
en: IN STD_LOGIC;
y: OUTSTD_LOGIC_VECTOR(7 downto 0));
ENDdec3to8;
ARCHITECTUREbehavior OFdec3to8 IS
BEGIN
PROCESS (x,en)
BEGIN
y <=”11111111”;
IF (en = ’1’)THEN
CASE x ISWHEN”000” =>y(0)<= ’0’;
WHEN”001” =>y(1)<= ’0’;
WHEN”010” =>y(2)<= ’0’;
WHEN”011” =>y(3)<= ’0’;
WHEN”100” =>y(4)<= ’0’;
WHEN”101” =>y(5)<= ’0’;
WHEN”110” =>y(6)<= ’0’;
WHEN”111” =>y(7)<= ’0’;
END CASE;
END IF;
END PROCESS;
ENDbehavior;
Söû duïng
PROCESS
NguyenTrongLuat 47
Phaùt bieåu
If ….
Case ….
BOÄ GIAÛI MAÕ
3 →8

48. LIBRARYieee;
USEieee.std_logic_1164.all;
USEieee.std_logic_arith.all;
USEieee.std_logic_unsigned.all;
ENTITYdecode38 IS
PORT( x: IN STD_LOGIC_VECTOR(2 downto 0);
y: OUT STD_LOGIC_VECTOR(0 to 7));
ENDdecode38;
ARCHITECTUREbehavior OFdecode38 IS
BEGIN
PROCESS(x)
VARIABLEj: integer;
BEGIN
j:= CONV_INTEGER(x);
FORiIN0 to 7 LOOP
IF(i= j) THEN
y(i)<= ’0’;
ELSE y(i)<= ’1’;
ENDIF;
ENDLOOP;
ENDPROCESS;
ENDbehavior;
Söû duïng
PROCESS
Phaùt bieåu
For …. loop
NguyenTrongLuat 48
Söû duïng haøm CONV_INTEGERñeå ñoåi döõ
lieäu kieåu STD_LOGIC_VECTOR thaønh kieåu
INTEGER.
Ñeå söû duïng haøm naøy, trong phaàn LIBRARY
caàn phaûi khai baùo goùi (package)
-STD_LOGIC_ARITH
-STD_LOGIC_UNSIGNED
BOÄ GIAÛI MAÕ
3 →8

49. NguyenTrongLuat 49
BOÄ MAÕ HOÙA ÖU TIEÂN
E
N
C
O
D
E
R
i3 i2 i1 i0x1 x0 v
0 0 0 0
0 0 0 1
0 0 1 X
0 1 X X
1 X X X
d d 0
0 0 1
0 1 1
1 0 1
1 1 1
i0
i1
i2
i3
x0
x1
v
encoder
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYencoderIS
PORT( i: INSTD_LOGIC_VECTOR(3 downto 0);
x: OUTSTD_LOGIC_VECTOR(1 downto 0);
v : OUTSTD_LOGIC);
ENDencoder;
ARCHITECTUREflow OFencoder IS
BEGIN
x <=”11”WHENi(3) =’1’ ELSE
”10”WHENi(2) =’1’ ELSE
”01”WHENi(1) =’1’ ELSE
”00”;
v<= ’0’ WHENi= ”0000”
ELSE ’1’;
ENDflow;
WITH i SELECT
x <=”00”WHEN”0001” ,
”01”WHEN”0010”|”0011”,
”10”WHEN”0100”
to ”0111”,
”11”WHEN OTHERS;
WITH i SELECT
V<=’0’ WHEN”0000”,
’1’ WHEN OTHERS;

50. NguyenTrongLuat 50
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYencoder2IS
PORT( i: INSTD_LOGIC_VECTOR(3 downto 0);
x: OUTSTD_LOGIC_VECTOR(1 downto 0);
v : OUTSTD_LOGIC);
ENDencoder2;
ARCHITECTUREbehavior OFencoder2 IS
BEGIN
PROCESS(i)
BEGIN
IFi(3) =’1’ THEN x <=”11”;
ELSIFi(2) =’1’THEN
x <=”10”;
ELSIFi(1) =’1’THEN
x <=”01”;
ELSIFx <=”00”;
ENDIF;
ENDPROCESS;
v<= ’0’ WHENi= ”0000”
ELSE ’1’;
ENDbehavior;
PROCESS(i)
BEGIN
x<= ”00”;
IFi(1)=’1’ THEN x <=”01”;
END IF;
IFi(2)=’1’ THEN x <=”10”;
END IF;
IFi(3)=’1’ THEN x <=”11”;
END IF;
v<= ’1’;
IFi=”0000” THENv <=’0’;
ENDIF;
ENDPROCESS;
Söû duïng
PROCESS

51. NguyenTrongLuat 51
BOÄ SO SAÙNHC
O
M
P
A
R
A
T
O
R
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYcompareIS
PORT(a, b: INSTD_LOGIC_VECTOR(3 downto 0);
aeqb, agtb, altb : OUTSTD_LOGIC);
ENDcompare;
ARCHITECTUREbehavior1 OFcompare IS
BEGIN
aeqb <=’1’ WHEN a =b ELSE’0’;
agtb <=’1’ WHEN a >b ELSE’0’;
altb <=’1’ WHEN a <b ELSE’0’;
ENDbehavior1;
ARCHITECTUREbehavior2 OFcompare IS
BEGIN
PROCESS (a, b)
BEGIN
aeqb<=’0’; agtb<=’0’; altb<=’0’;
IF a =b THEN aeqb<=’1’; ENDIF;
IF a >b THEN agtb<=’1’; ENDIF;
IF a <b THEN altb<=’1’; ENDIF;
END PROCESS;
ENDbehavior2;
BOÄ SO SAÙNH 4 BIT

52. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYledIS
PORT( bcd: INSTD_LOGIC_VECTOR(3 downto 0);
segs : OUTSTD_LOGIC_VECTOR(6 downto 0);
ENDled;
ARCHITECTUREBehavioral OFled IS
BEGIN
PROCESS(bcd)
BEGIN
CASEbcdIS --abcdefg
WHEN"0000" =>segs<= "1111110";
WHEN"0001" =>segs<= "0110000";
WHEN"0010" =>segs<= "1101101";
WHEN"0011" =>segs<= "1111001";
WHEN"0100" =>segs<= "0110011";
WHEN"0101" =>segs<= "1011011";
WHEN"0110" =>segs<= "1011111";
WHEN"0111" =>segs<= "1110000";
WHEN"1000" =>segs<= "1111111";
WHEN"1001" =>segs<= "1111011";
WHEN OTHERS=>segs<= "0000000";--ALL OFF
ENDCASE;
ENDPROCESS;
ENDBehavioral;
BOÄ GIAÛI MAÕ
LED 7 ÑOAÏN
B
C
D
T
O
7
S
E
G
S
NguyenTrongLuat 52

53. THIEÁT KEÁ HEÄ TUAÀN TÖÏ BAÈNG VHDL
-Heä tuaàn töï chæ ñöôïc thöïc hieän baèng caùc phaùt bieåu tuaàn töï
(sequential statement).
-Thöïc hieän: maïch choát, FF, thanh ghi, boä ñeám, maùy traïng
thaùi.
-Bieán (Variable)chæ toàn taïi cuïc boä trong Process, vì vaäy muoán
laáy giaù trò cuûa bieán ra ngoaøi Processthì ta phaûi gaùn bieán cho
tín hieäu (Signal).
NguyenTrongLuat 53
-Trong Process, bieán ñöôïc caäp nhaät giaù trò sau moãi phaùt bieåu;
coøn tín hieäu chæ ñöôïc caäp nhaät ôû cuoái Process.

54. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYDlatchIS
PORT(D,Clk: INSTD_LOGIC;
Q,Qn : OUTSTD_LOGIC);
ENDDlatch;
ARCHITECTUREbehavior OFDlatch IS
BEGIN
PROCESS (D,Clk)
BEGIN
IF Clk=’1’THEN
Q<=D;
Qn <=NOT Q;
END IF;
END PROCESS;
ENDbehavior;
D
Clk
Q
Q
Dlatch
clk DQ
+
Q
+
0 XQ Q
1 0
1 1
0 1
1 0
NguyenTrongLuat 54
MAÏCH CHOÁT

55. NguyenTrongLuat 55
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYDflipflopIS
PORT(D,Clk: INSTD_LOGIC;
Q,Qn : OUTSTD_LOGIC);
ENDDflipflop;
ARCHITECTUREbehavior OFDflipflop IS
BEGIN
PROCESS (Clk)
BEGIN
IF Clk’eventANDClk=’1’THEN
Q<=D;
Qn <=NOT Q;
END IF;
END PROCESS;
ENDbehavior;
D
clk
Q
Q
Dflipflop
FLIP -FLOP
-clk’event phaùt hieän söï thay ñoåi tín hieäu clktöø 0 leân 1 hoaëc töø 1 veà 0.
-Goùi std_logic_1164coù ñònh nghóa 2 haøm (function): rising_edge ñeå phaùt
hieän caïnh leân vaø falling_edgeñeå phaùt hieän caïnh xuoáng cuûa tín hieäu.
IFrising_edge(clk) THEN

56. NguyenTrongLuat 56
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYDFFIS
PORT(D,Clk, Pr, Cl: INSTD_LOGIC;
Q,Qn : OUTSTD_LOGIC);
ENDDFF;
ARCHITECTUREbehavior OFDFF IS
BEGIN
PROCESS (Clk, Pr, Cl)
BEGIN
IF Pr= ’0’THEN Q<=’1’;
Qn <=’0’;
ELSIF Cl= ’0’THEN Q<=’0’;
Qn <=’1’;
ELSIF Clk’eventANDClk=’0’THEN
Q<=D;
Qn <=NOT Q;
END IF;
END PROCESS;
ENDbehavior;
D
Clk
Q
Q
DFF
Pr
Cl

57. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYregn IS
GENRERIC(n: NATURAL := 4);
PORT(D: IN STD_LOGIC_VECTOR(n -1 downto 0);
Clk, Reset: _VECTORIN STD_LOGIC;
Q: OUT STD_LOGIC(n-1 downto 0));
ENDregn;
ARCHITECTUREbehavioral OFregn IS
BEGIN
PROCESS(Clk, Reset, D)
BEGIN
IF(Reset= '0') THEN
Q<= (others => '0');
ELSIFrising_edge(Clock) THEN
Q<= D;
ENDIF;
ENDPROCESS;
ENDbehavioral;
Q <= (Others=> ‘0’) töông ñöông vôùi Q <= “0000”
GENRERIC(n: NATURAL := 4)
Khai baùo generic nlaø natural (soá nguyeân döông)
NguyenTrongLuat 57
D
Clk
Q
regn
Reset
n n
Thanh ghi (register)

58. NguyenTrongLuat 58
BOÄ ÑEÁM (COUNTER)
Söû duïng bieán countñeå thöïc hieän chöùc naêng boä ñeám
LIBRARYieee;
USEieee.std_logic_1164.all
USEieee.std_logic_unsigned.all;
ENTITYUpcnt4 IS
PORT(Clk, Rst: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 downto 0));
ENDUpcnt4;
ARCHITECTUREBehavioral OFUpcnt4 IS
BEGIN
PROCESS(Clk, Rst)
VARIABLEcount: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
IFRst='1' THEN
count := (others=>'0');
ELSIFrising_edge(clk) THEN
count := count + "0001";
ENDIF;
Q <= count;
ENDPROCESS;
ENDBehavioral;
BOÄ ÑEÁM LEÂN 4 BIT
coù Reset baát ñoàng boä
Bieán countñöôïc gaùn cho ngoõ ra Q ôû cuoái Process, vì
bieán laø giaù trò cuïc boä trong Process
Rst
Clk
Q0
Upcnt4
Q1
Q2
Q3

59. LIBRARYieee;
USEieee.std_logic_1164.all
USEieee.std_logic_unsigned.all;
ENTITYUpcnt4 IS
PORT( Clk, Rst: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 downto 0));
ENDUpcnt4;
ARCHITECTUREBehavioral OFUpcnt4 IS
SIGNALcount: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS(Clk, Rst)
BEGIN
IFrising_edge(clk) THEN
IFRst='1' THEN
count <= (others=>'0');
ELSE
count <= count + "0001";
ENDIF;
ENDIF;
ENDPROCESS;
Q <= count;
ENDBehavioral;
NguyenTrongLuat 59
Boä ñeám
coù reset
ñoàng boä
Söû duïng tín hieäu countthay cho bieán count.
Tín hieäu countñöôïc gaùn cho ngoõ ra Q beân
ngoaøi Process.

60. LIBRARYieee;
USEieee.std_logic_1164.all
USEieee.std_logic_unsigned.all;
ENTITYUpcnt10 IS
PORT( Clk, Rst: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 downto 0));
ENDUpcnt10;
ARCHITECTUREBehavioral OFUpcnt10 IS
BEGIN
PROCESS(Clk, Rst)
VARIABLEcount: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
IFRst='1' THEN
count := (others=>'0');
ELSIFrising_edge(clk) THEN
IFcount= "1001" then
count:= (others=>'0');
ELSEcount := count + "0001";
ENDIF;
ENDIF;
Q <= count;
ENDPROCESS;
ENDBehavioral;
NguyenTrongLuat 60
BOÄ ÑEÁM LEÂN
THAÄP PHAÂN

61. NguyenTrongLuat 61
LIBRARYieee;
USEieee.std_logic_1164.all
USEieee.std_logic_unsigned.all;
ENTITYUpdncnt4 IS
PORT( Clk, Rst, Updn: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(3 downto 0));
ENDUpdncnt4;
ARCHITECTUREBehavioral OFUpdncnt4 IS
SIGNALcount: STD_LOGIC_VECTOR (3 downto 0);
BEGIN
PROCESS(Clk, Rst)
BEGIN
IFRst= ’1’ THEN
count <= (others =>’0’);
ELSIFrising_edge(Clk) THEN
IFUpdn= ’1’ THEN
count <= count + ”0001”;
ELSEcount <= count -”0001”;
ENDIF;
ENDIF;
ENDPROCESS;
Q <= count;
ENDBehavioral;
BOÄ ÑEÁM 4 bit
LEÂN / XUOÁNG
Updn
Clk
Q0
Updncnt4
Rst
Q1
Q2
Q3

62. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYsipo IS
GENERIC(n: NATURAL := 8);
PORT(Serin, Clk: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(
n-1 downto 0));
ENDsipo;
ARCHITECTUREshiftreg OFsipo IS
SIGNALreg: STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS(Clk)
BEGIN
IFrising_edge(Clk) THEN
reg<= reg(n-2downto0)& Serin;
ENDIF;
ENDPROCESS;
Q<= reg;
ENDshiftreg;
Thanh ghi dòch (shift reg.)
NguyenTrongLuat 62
S
I
P
O
Serin
Clk
Q
sipo
n

63. LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYsiso IS
GENERIC(n: NATURAL := 8);
PORT(Clk, Serin: IN STD_LOGIC;
Serout: OUT STD_LOGIC);
ENDsiso;
ARCHITECTUREshiftreg OFsiso IS
SIGNALreg: STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS(Clk)
BEGIN
IFrising_edge(Clk) THEN
reg<= reg(n-2downto0)& Serin;
ENDIF;
ENDPROCESS;
Serout<= reg(n-1);
ENDshiftreg;
NguyenTrongLuat 63
S
I
S
O
Serin
Clk
siso
Serout

64. O
NguyenTrongLuat 64
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYpiso IS
GENERIC(n: NATURAL := 8);
PORT(Serin, Clk, ShLd: IN STD_LOGIC;
D: IN STD_LOGIC_VECTOR(n -1 downto 0);
Serout : OUT STD_LOGIC);
ENDpiso;
ARCHITECTUREshiftreg OFpiso IS
SIGNALreg: STD_LOGIC_VECTOR(n-1 downto 0);
BEGIN
PROCESS(Clk)
BEGIN
IFrising_edge(Clk) THEN
IF ShLd= ’0’THEN
reg<=D;
ELSE reg<= reg(n-2downto0)& Serin;
ENDIF;
ENDPROCESS;
Serout<= reg(n-1);
ENDshiftreg;
S
I
P
D
Clk
Serout
piso
n
ShLd
Serin

65. -Maùy traïng thaùi höõu haïn ñöôïc thieát keá deã daøng baèng phaùt
bieåu PROCESS.
-Vieäc chuyeån traïng thaùi ñöôïc moâ taû trong Process vôùi danh
saùch caûm nhaän (sensitivity list) laø clockvaø tín hieäu resetbaát
ñoàng boä.
-Ngoõ ra coù theå ñöôïc moâ taû baèng caùc phaùt bieåu ñoàng thôøi
(concurrenrt) naèm ngoaøi process.
-Coù 2 kieåu FSM: MOOREvaø MEALY
NguyenTrongLuat 65
MAÙY TRAÏNG THAÙI
FSM

66. MOORE
FSM
Present State
Register
Next State
function
Output
function
Inputs
Present State
Next State
Outputs
clock
reset
Next state function:haøm traïng thaùi keá tieáp laø maïch toå hôïp phuï
thuoäc vaøo ngoõ vaøo vaø traïng thaùi hieän taïi
Output function:haøm ngoõ ra laø maïch toå hôïp phuï thuoäc vaøo traïng
thaùi hieän taïi
Present State Register:thanh ghi traïng thaùi hieän taïi löu giöõ 1
traïng thaùi hieän taïi, seõ chuyeån traïng thaùi khi coù xung clock.
NguyenTrongLuat 66

67. Present State
Register
Next State
function
Output
function
Inputs
Present State
Next State
Outputs
clock
reset
Process Thanh ghi traïng thaùi:
PROCESS (reset, clock)
Process Haøm traïng thaùi keá tieáp:
PROCESS (input, present_state)
Process Haøm ngoõ ra:
PROCESS (present_state)
Concurrent Statements
FSM kieåu MOORE ñöôïc moâ taû baèng 3 PROCESS
-Process Haøm ngoõ ra coù theå thay theá baèng caùc phaùt bieåu
ñoàng thôøi (concurrent statement)
NguyenTrongLuat 67
-Process 2 vaø 3 coù theå keát hôïp thaønh 1 Process.

68. LIBRARY ieee;
USE iee.std_logic_1164.all;
ENTITY Moore_FSM IS
PORT (clock, rerset, input: IN std_logic;
output: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behaviorOF Moore_FSMIS
TYPE stateIS (list of states);
SIGNAL pr_state, nx_state:state;
BEGIN
PROCESS(clk, reset)
BEGIN
IF reset= ’1’THEN
pr_state<= reset state;
ELSIF (clock= ’1’ and clock’event)THEN
pr_state<= nx_state;
END IF;
END PROCESS;
TYPEstateIS(list of states): khai baùo state laø döõ lieäu kieåu lieät keâ
NguyenTrongLuat 68
Process Thanh ghi traïng thaùi:
PROCESS (reset, clock)

69. PROCESS (input, ps_state)
CASE ps_stateIS
WHEN state_1=>
IF input= ’…’THEN
nx_state<=state_2;
ELSIF nx_state<=state_3;
END IF;
WHEN state_2=>
IF input= ’…’THEN
nx_state<=state_1;
ELSIF nx_state<=state_3;
END IF;
. . .
END CASE;
END PROCESS;
NguyenTrongLuat 69
Process Haøm traïng thaùi keá tieáp:
PROCESS (input, present_state)

70. PROCESS(ps_state)
CASE ps_stateIS
WHEN state_1=>
output<=’...’;
WHEN state_2=>
output<= ’...’;
...
END CASE;
END PROCESS;
Coù theå duøng phaùt bieåu IF… THEN…
NguyenTrongLuat 70
Process Haøm ngoõ ra:
PROCESS (present_state)
Coù theå thay theá process naøy baèng phaùt bieåu ñoàng thôøi
output<= ... ;

71. TT
hieän taïi
TT keá tieápNgoõ ra
(z)
x = 0x = 1
LIBRARY ieee;
USE iee.std_logic_1164.all;
ENTITY Moore_FSM IS
PORT (
clock, rerset, x: IN std_logic;
z: OUT std_logic);
END Moore_FSM;
ARCHITECTURE behaviorOF Moore_FSMIS
TYPE stateIS (S0,S1,S2,S3);
SIGNAL pr_state, nx_state:state;
BEGIN
regst:PROCESS(clk, reset)
BEGIN
IF reset= ’1’THEN pr_state<= S0;
ELSIF (clock= ’1’ and clock’event)THEN
pr_state<= nx_state;
END IF;
END PROCESS;
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
NguyenTrongLuat 71

72. nxst:PROCESS (x, ps_state)
CASE ps_stateIS
WHEN S0=>
IF x= ’0’THEN
nx_state<=S0;
ELSIF nx_state<=S1;
END IF;
WHEN S1=>
IF x= ’0’THEN nx_state<=S2;
ELSIF nx_state<=S1;
END IF;
WHEN S2=>
IF x= ’0’THEN nx_state<=S0;
ELSIF nx_state<=S3;
END IF;
WHEN S3=>
IF x= ’0’THEN nx_state<=S2;
ELSIF nx_state<=S1;
END IF;
END CASE;
END PROCESS;
TT
hieän taïi
TT keá tieápNgoõ ra
(z)
x = 0x = 1
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
NguyenTrongLuat 72

73. TT
hieän taïi
TT keá tieápNgoõ ra
(z)
x = 0x = 1
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
Output:PROCESS(ps_state)
CASE ps_stateIS
WHEN S3=>
z<=’1’;
WHEN OTHERS =>
z<= ’0’;
END CASE;
END PROCESS;
ENDbehavior;
Output: PROCESS(ps_state)
IF ps_state=S3THEN z<=’1’;
ELSE’0’;
END IF;
z<=’1’ WHEN ps_state=S3ELSE’0’;
NguyenTrongLuat 73

74. NguyenTrongLuat 74
Keát hôïp Process 2 vaø 3 thaønh 1 Process
TT
hieän taïi
TT keá tieápNgoõ ra
(z)
x = 0x = 1
S0
S1
S2
S3
S0
S2
S0
S2
S1
S1
S3
S1
0
0
0
1
nx_out:PROCESS (x, ps_state)
CASE ps_stateIS
WHEN S0=>
z<=’0’;
IF x= ’0’THEN
nx_state<=S0;
ELSIF nx_state<=S1;
END IF;
WHEN S1=>
z<=’0’;
IF x= ’0’THEN nx_state<=S2;
ELSIF nx_state<=S1; END IF;
WHEN S2=>
z<=’0’;
IF x= ’0’THEN nx_state<=S0;
ELSIF nx_state<=S3; END IF;
WHEN S3=>
z<=’1’;
IF x= ’0’THEN nx_state<=S2;
ELSIF nx_state<=S1; END IF;
END CASE;
END PROCESS;
ENDbehavior;

75. Present State
Present State
Register
Next State
function
Output
function
Inputs
Next State
Outputs
clock
reset
Process Thanh ghi traïng thaùi:
PROCESS (reset, clock)
Process Haøm traïng thaùi keá tieáp
vaø Ngoõ ra:
PROCESS (input, present_state)
FSM kieåu MEALY ñöôïc moâ taû baèng 2 PROCESS
NguyenTrongLuat 75
MEALY
FSM

76. PROCESS (input, ps_state)
CASE ps_stateIS
WHEN state_1=>
IF input= ’…’THEN
output<=’...’;
nx_state<=state_2;
ELSIF
output<=’...’;
nx_state<=state_3;
END IF;
. . .
END CASE;
END PROCESS;
NguyenTrongLuat 76
Process Haøm traïng thaùi keá tieáp vaø Ngoõ ra:
PROCESS (input, present_state)

77. nx_out:PROCESS (x, ps_state)
CASE ps_stateIS
WHEN S0=>
IF x= ’0’THEN
z<=’0’;
nx_state<=S0;
ELSIF
z<=’0’;
nx_state<=S1;
END IF;
WHEN S1=>
IF x= ’0’THEN
z<=’0’;
nx_state<=S2;
ELSIF
z<=’0’;
nx_state<=S1;
END IF;
WHEN S2=>
IF x= ’0’THEN
z<=’0’;
nx_state<=S2;
ELSIF
z<=’0’;
nx_state<=S1;
END IF;
END CASE;
END PROCESS;
TT
HT
TT keá tieápNgoõ ra (Z)
X = 01X = 01
S0
S1
S2
S0
S2
S2
S1
S1
S1
0
0
0
0
0
1
NguyenTrongLuat 77

78. -Vieäc gaùn traïng thaùi thöôøng laø töï ñoäng.
-Ta coù 2 caùch ñeå gaùn cho moãi traïng thaùi baèng 1 toå hôïp nhò phaân:
TYPE stateIS (S0,S1,S2);
SIGNAL pr_state, nx_state:state;
TYPE stateIS STD_LOGIC_VECTOR(1 downto 0);
CONSTANTS0: state:= ”00”;
CONSTANTS1: state:= ”01”;
CONSTANTS2: state:= ”11”;
SIGNAL pr_state, nx_state:state;
* Söû duïng thuoäc tính (attribute) enum_encoding:
TYPE stateIS (S0,S1,S2);
ATTRIBUTEENUM_ENCODING: STRING;
ATTRIBUTEENUM_ENCODING OFstate: TYPEIS”00 01 11”;
SIGNAL pr_state, nx_state:state;
Gán trạng thái
* Khai baùo constant
NguyenTrongLuat 78

79. Phaùt bieåu WAIT
-WAIT laø phaùt bieåu tuaàn töï (sequential statement).
-Neáu Process khoâng coù danh saùch caûm nhaän (sensitivity list)
thì phaùt bieåu WAIT laø phaùt bieåu ñaàu tieân cuûa Process
WAITUNTILcondition_signal;
WAITONsensitivity_list;
WAITFORtime;
Process ñöôïc thöïc thi khi coù söï thay ñoåi giaù trò cuûa 1 hoaêc
nhieàu tín hieäu trong danh saùch caûm nhaän
Process ñöôïc thöïc thi khi coù ñieàu kieän cuûa 1 tín hieäu xaåy ra
(true)
Chæ duøng trong moâ phoûng (testbench). Taïm döøng thöïc hieän
Process trong 1 khoaûng thôøi gian (time).
NguyenTrongLuat 79

80. NguyenTrongLuat 80
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYDlatchIS
PORT(D,Clk: INSTD_LOGIC;
Q,Qn : OUTSTD_LOGIC);
ENDDlatch;
ARCHITECTUREbehavior OFDlatch IS
BEGIN
PROCESS (D,Clk)
BEGIN
IF Clk=’1’THEN
Q<=D;
Qn <=NOT Q;
END IF;
END PROCESS;
ENDbehavior;
ARCHITECTUREbehavior OFDlatch IS
BEGIN
PROCESS
BEGIN
WAIT ON Clk,D;
IF Clk=’1’THEN
Q<=D;
Qn <=NOT Q;
END IF;
END PROCESS;
ENDbehavior;
D
Clk
Q
Q
Dlatch

81. NguyenTrongLuat 81
LIBRARYieee;
USEieee.std_logic_1164.all;
ENTITYDflipflopIS
PORT(D,Clk: INSTD_LOGIC;
Q,Qn : OUTSTD_LOGIC);
ENDDflipflop;
ARCHITECTUREbehavior OFDflipflop IS
BEGIN
PROCESS (Clk)
BEGIN
IF Clk’eventANDClk=’1’THEN
Q<=D;
Qn <=NOT Q;
END IF;
END PROCESS;
ENDbehavior;
ARCHITECTUREbehavior OFDflipflop IS
BEGIN
PROCESS
BEGIN
WAIT UNTIL Clk’eventANDClk=’1’;
Q<=D;Qn <=NOT Q;
END PROCESS;
ENDbehavior;
D
clk
Q
Q
Dflipflop