pitch - sequoia capital ventures format.pptx

pitch for my product using Sequoia Capital format.

1. Octopus Design Automation Michael Green

2. Company Purpose Octopus Design Automation develops software to automate the verification of the world’s most advanced System On-Chip Devices.

3. What is the problem?

4. Developing ASIC and FPGA-based products is hard

5. To develop a chip requires hiring more people to spend more time doing design verification

6. The majority of ASIC and FPGA design projects complete behind schedule and the design verification piece is a significant contributor to project slips. 3

7. An essential part of chip verification is achieving functional coverage closure

8. The state of the art in functional coverage closure employs a process that is highly manual, error prone, and can only scale by making your DV team larger or making your DV team work longer.

9. Design Specification Design Engineer Test Plan Verification Goals Test Directives Tests Tests Tests Tests Verif . Engineer Verif. Engineer Test Generator Simulator Coverage Results Verif. Engineer RTL Verif. Engineer The Painful Process of Hitting Functional Coverage Closure

10. Octopus Design Automation’s Flow Employs a Learning Test Generator to automate achieving functional coverage closure

11. Design Specification Design Engineer Verif. Engineer RTL Test Plan Verification Goals Verif. Engineer Learning Test Generator Tests Tests Tests Tests Simulator Coverage Results Automatic Functional Coverage Closure

12. Pain and Relief of Pain What is painful about functional coverage closure? It requires repetitive manual intervention to analyze the Coverage Information, update the Test Plan, and the Test Directives in the hope of achieving better coverage closure What pain is the solution relieving? It eliminates the need for manual intervention to iteratively refine stimulus to achieve coverage goals It uses a test generator that learns how to generator better stimulus over time to hit your coverage goals

13. Solution (Concept Phase) It’s an application that plugs into your existing HDL simulator I takes as input your design, your functional coverage goals, and your test bench and generates stimulus that reaches your goals Leverages patent-pending hybrid formal analysis machine learning engine to train and generate an intelligent test generator Uses a subset of your verification goals as inputs for training The resultant Learning Based Test Generator can be integrated into your test bench like any other verification component

14. TAM, SAM, SOM The learning goal based generator will be a new class of verification IP It will be automatic functional coverage closure as a service software that is an add-on to an event-based simulator or formal property analysis tool The product will be disruptive to design services companies Design services TAM in Q4 2016 was $118M, thus assuming $472M per year 4 Based on design services TAM and % time a design engineer spends on functional coverage closure, SAM is $104M per year There are no companies that provide an automatic functional coverage closure tool, hence SOM is $104M per year.

15. Competitors Synopsys, Cadence, Siemens (Mentor Graphics):  #1, #2, and #3 Suppliers of EDA software in the world Have significant resources they could wield to address this competitive threat to their design services businesses Could potentially offer to acquire the company as this software does not replace their products but is an add-on to their software that could potentially drive increased license utilization and eventually drive license growth at their respective customers Design Services Companies: Intrinsix , TVS, Truchip Could react with help from EDA companies Breker Verification Systems or One Spin Solution: May react to protect its graph-based or formal verification systems

16. Business Model Depends on the type of usage Traditional pricing model: Per instance licenses that have to be renewed every year. $X/(year*instance) Pretrained agent in the cloud with data sharing: $Y/(test generated using pre-trained agent)

17. Team Founder Michel Green 20 years design and verification experience overall in the semiconductor industry Worked as a design or verification engineer at Intel Corporation for 9.6 years 10 years at various CPU Silicon IP companies, startups Synopsys MIPS Technologies Cadence Design Systems Tensilica P.A. Semiconductor Samsung Research America AMD

18. Footnotes 1 https://blogs.mentor.com/verificationhorizons/blog/2016/08/22/part-2-the-2016-wilson-research-group-functional-verification-study/ 2 https://blogs.mentor.com/verificationhorizons/blog/2016/10/04/part-8-the-2016-wilson-research-group-functional-verification-study/ 3 http://events.dvcon.org/2015/proceedings/papers/10_1.pdf 4 ESDA MSS Newsletter Q4 2017