Placement

Placement is a very important stage of physical design where all the standard cells get placed inside the core boundary. Overall QoR of the design greatly depends on the fact that how well placement is done. You must have noticed that the placement stage takes quite a large runtime. Actually, the tool performs various steps in a sequence to complete the placement stage. In this article, we will try to understand what are the important steps and the order in which the EDA tools perform to complete the placement stage.

Placement is the process of placing the standard cells inside the core boundary in an optimal location. The tool tries to place the standard cell in such a way that the design should have minimal congestions and the best timing. Every PnR tool provides various commands/switches so that users can optimize the design in a better way in terms of timing, congestion, area, and power as per their requirements. Based on the preferences set by the user, the tool tray to place and optimize it for better QoR. Placement does not place only the standard cells present in the synthesized netlist but also places many physical only cells and adds buffers/inverters as per the requirement to meet the timings, DRV, and foundry requirements. Here are the basic steps which the tool performs during the placement and optimization stage.

1. Intro
Placement
How to Plan your own chip
Ahmed Abdelazeem
Faculty of Engineering
Zagazig University
RTL2GDSII Flow, February 2022
Ahmed Abdelazeem ASIC Physical Design

2. Intro
Table of Contents
1Introduction
2Timing Driven Placement
3Congestion Driven Placement
4High Fanout Synthesis (HFS)
5Scan Chain Reordering
6Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

3. Intro Place
Table of Contents
1Introduction
2Timing Driven Placement
3Congestion Driven Placement
4High Fanout Synthesis (HFS)
5Scan Chain Reordering
6Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

4. Intro Place
Design Status Prior to Placement
Design Planning is completed
Second-Pass Synthesis is completed
Second-Pass Data Setup is completed
“Floorplanned cell” is generated- ready for placement
1Core and periphery areas defined
2Macros are placed and “fixed”
3Placement blockages defined
4Power grid pre-routed
5Standard cell placement is discarded
Ahmed Abdelazeem ASIC Physical Design

5. Intro Place
Placement Problem
The goal of placement is to minimize the total area and
interconnect cost.
The quality of the attainable routing is
highly determined by the placement.
Circuit placement becomes very critical in
65nm and below technologies.
Ahmed Abdelazeem ASIC Physical Design

6. Intro Place
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Inputs: 1Netlist of gates and wires.
2Floorplan and Technology constraints
Outputs:
1All cells located in the floorplan.
Goals:
1Provide legal location of entire netlist
2Enable detailed route of all nets
3Meet timing, area, and power targets
Ahmed Abdelazeem ASIC Physical Design

7. Intro Place
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Inputs: 1Netlist of gates and wires.
2Floorplan and Technology constraints
Outputs:
1All cells located in the floorplan.
Goals:
1Provide legal location of entire netlist
2Enable detailed route of all nets
3Meet timing, area, and power targets
Ahmed Abdelazeem ASIC Physical Design

8. Intro Place
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Inputs: 1Netlist of gates and wires.
2Floorplan and Technology constraints
Outputs:
1All cells located in the floorplan.
Goals:
1Provide legal location of entire netlist
2Enable detailed route of all nets
3Meet timing, area, and power targets
Ahmed Abdelazeem ASIC Physical Design

9. Intro Place
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Inputs: 1Netlist of gates and wires.
2Floorplan and Technology constraints
Outputs:
1All cells located in the floorplan.
Goals:
1Provide legal location of entire netlist
2Enable detailed route of all nets
3Meet timing, area, and power targets
Ahmed Abdelazeem ASIC Physical Design

10. Intro Place
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Inputs: 1Netlist of gates and wires.
2Floorplan and Technology constraints
Outputs:
1All cells located in the floorplan.
Goals:
1Provide legal location of entire netlist
2Enable detailed route of all nets
3Meet timing, area, and power targets
Ahmed Abdelazeem ASIC Physical Design

11. Intro Place
Placement
Placement is the stage of the design flow, during which each
standard cell is given an exact location
Placement does not just place the standard cell available in
the synthesized netlist, it also optimized the design.
Inputs: 1Netlist of gates and wires.
2Floorplan and Technology constraints
Outputs:
1All cells located in the floorplan.
Goals:
1Provide legal location of entire netlist
2Enable detailed route of all nets
3Meet timing, area, and power targets
Ahmed Abdelazeem ASIC Physical Design

12. Intro Place
Global and Detailed Placement
In general, most tools partition the placement task into two
stages:
Ahmed Abdelazeem ASIC Physical Design

13. Intro Place
Global Placement
Standard cells must be in groups in such a way that the
number of connections between groups is minimum
This issue is solved through circuit partitioningAs a basic criterion, the minimum is taken among group
connections
Ahmed Abdelazeem ASIC Physical Design

14. Intro Place
Global Placement
Standard cells must be in groups in such a way that the
number of connections between groups is minimum
This issue is solved through circuit partitioningAs a basic criterion, the minimum is taken among group
connections
Ahmed Abdelazeem ASIC Physical Design

15. Intro Place
Global Placement
Standard cells must be in groups in such a way that the
number of connections between groups is minimum
This issue is solved through circuit partitioningAs a basic criterion, the minimum is taken among group
connections
Ahmed Abdelazeem ASIC Physical Design

16. Intro Place
Detailed Placement
As a rule, detailed placement
is solved in two stages:
1Coarse placement
2Legalization of cell
placement
Ahmed Abdelazeem ASIC Physical Design

17. Intro Place
Coarse placement
In a coarse placement all the cells are placed in the
approximate locations but they are not legally placed.
Cells overlap and are not on-grid.
Large cells (e.g. RAMs) form large placement blockages for
other smaller leaf cells.
Power routing forms routing layer blockages that will also be
checked and avoided if specified.
Ahmed Abdelazeem ASIC Physical Design

18. Intro Place
Legalize Cell Placement
Provide a legal placement for each instance with no overlap
Try and minimize wirelength (or other cost metrics)
Try to finish with uncongested design
Ahmed Abdelazeem ASIC Physical Design

19. Intro Timing
Table of Contents
1Introduction
2Timing Driven Placement
3Congestion Driven Placement
4High Fanout Synthesis (HFS)
5Scan Chain Reordering
6Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

20. Intro Timing
Timing-Driven Placement (1)
All steps including placement are
timing-driven
Timing-driven placement tries to
place critical path cells close
together to reduce net RCs and to
meet setup timing
RCs are based on Virtual Route
(VR)
Ahmed Abdelazeem ASIC Physical Design

21. Intro Timing
Timing-Driven Placement (2)
Timing-driven placement
based on Virtual Route
Tries to place cells along
timing-critical paths close
together to reduce net
RCs and meet setup
timing
Net RCs are based on
Virtual Routing (VR)
estimates
Ahmed Abdelazeem ASIC Physical Design

22. Intro Timing
Timing-Driven Placement (3)
Standard cells are placed in “placement rows”
Cells in a timing-critical path are placed close together to
reduce routing-related delays→Timing-Driven Placement
Ahmed Abdelazeem ASIC Physical Design

23. Intro Timing
TDP: Estimating Rnet and Cnet Before Placement
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24. Intro Congestion
-
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25. Intro Congestion
Table of Contents
1Introduction
2Timing Driven Placement
3Congestion Driven Placement
4High Fanout Synthesis (HFS)
5Scan Chain Reordering
6Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

26. Intro Congestion
Congestion
Congestion occurs when the number of required routing tracks
exceeds the number of available tracks.
Congestion can be estimated from the results of a quick global
route.
Global bins with routing overflow can be identified
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27. Intro Congestion
Congestion Driven Placement: Routing resource
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28. Intro Congestion
Placement Issues with Congestion
If congestion is not too severe, the
actual route can be detoured
around the congested area
The detoured nets will have worse
RC delay compared to the VR
estimates
congested
In highly congested areas, delay estimates during placement will be
optimistic.
Ahmed Abdelazeem ASIC Physical Design

29. Intro Congestion
Non Routable on Severely Congested Design
It is important to minimize or
eliminate congestion before
continuing
Severe congestion can cause a
design to be un-routable
Ahmed Abdelazeem ASIC Physical Design

30. Intro Congestion
Congestion Calculation
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31. Intro Congestion
Congestion-driven Placement
It is important to minimize or
eliminate congestion before
continuing
Severe congestion can cause a
design to be un-routable
Ahmed Abdelazeem ASIC Physical Design

32. Intro Congestion
Congestion-driven Placement
Congestion Reduction
The tool tries to evaluate congestion hotspots and spread the
cells (lower utilization) in the area to reduce congestion.
The tool can also choose cell location based on congestion,
rather than wire-length.
Ahmed Abdelazeem ASIC Physical Design

33. Intro Congestion
Congestion vs. Timing-Driven Placement
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34. Intro Congestion
Global Route (GR) for Congestion Map
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35. Intro Congestion
Strategies to Fix Congestion
Modify the floorplan:
Mark areas for low utilization.
Top-level ports
Changing to a different metal layer
Spreading them out, re-ordering or moving to other sides
Macro location or orientation
Alignment of bus signal pins
Increase of spacing between macros
Add blockages and halos
Core aspect ratio and size
Making block taller to add more horizontal routing resources
Increase of the block size to reduce overall congestion
Power grid
Fixing any routed or non-preferred layers
Ahmed Abdelazeem ASIC Physical Design

36. Intro HFNS
Table of Contents
1Introduction
2Timing Driven Placement
3Congestion Driven Placement
4High Fanout Synthesis (HFS)
5Scan Chain Reordering
6Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

37. Intro HFNS
High Fanout Synthesis (HFS)
Ahmed Abdelazeem ASIC Physical Design

38. Intro HFNS
High Fanout Synthesis
What is fanout?
Fanout is the number of gate inputs to which the output can
be safely connected. i.e., The load that a gate output can
drive.
The maximum fanout of an output measures it’s load-driving
capability. Fanout belongs to the output.
What are High Fanout Nets(HFN) ?
High Fanout Nets are the nets which drive more number of
load. We set some max fanout limit by using the command
setmaxfanout
The nets which have greater than these limit are considered as
High Fanout Nets (HFN).
Generally clock nets, reset, scan, enable nets are High Fanout
Nets.
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39. Intro HFNS
What is High Fanout Net Synthesis (HFNS)?
High Fanout Net Synthesis (HFNS) is the process of buffering
the High Fanout Nets to balance the load.
To balance the load HFNS is perfomed.
Too many load affects delay numbers and transition times,
Because load is directly proportional to the delay.
Generally at placement step HFNS performed. HFNS can also
be performed at synthesis step using Design Compiler. But
it’s not good idea, Buffers will be removed during PD and
again HFNS is performed.
Care that should taken during HFNS:
1Make sure an appropriate fanout limit is set using
setmaxfanout
2Verify the SDC used for PD should not have idealnetwork
or donttouch
3Use ideal clock network – As clock nets are synthesized
separately during Clock Tree Synthesis (CTS) step, we set
clock network as ideal network.
Ahmed Abdelazeem ASIC Physical Design

40. Intro Scan Chain
Table of Contents
1Introduction
2Timing Driven Placement
3Congestion Driven Placement
4High Fanout Synthesis (HFS)
5Scan Chain Reordering
6Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

41. Intro Scan Chain
Pre-Existing Scan Chains?
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42. Intro Scan Chain
What’s the Issue with Existing Scan Chains?
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43. Intro Scan Chain
Placement Based Scan Chain Routing
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44. Intro Scan Chain
SCANDEF Reordering
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45. Intro Scan Chain
Partitioning with SCANDEF
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46. Intro Scan Chain
SCANDEF generated with DFTC
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47. Intro Scan Chain
Alpha-Numeric Ordering
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48. Intro Scan Chain
Reordering Within Scan-Chain
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49. Intro Scan Chain
Reordering Across Scan-Chains
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50. Intro Optimization
Table of Contents
1Introduction
2Timing Driven Placement
3Congestion Driven Placement
4High Fanout Synthesis (HFS)
5Scan Chain Reordering
6Placement Optimization
Ahmed Abdelazeem ASIC Physical Design

51. Intro Optimization
Optimization techniques
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52. Intro Optimization
Optimization techniques
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53. Intro Optimization
No Hold Time Fixing
By default opt
No hold time fixing
Hold time will be addressed during clock tree synthesis
All timing calculations are based on ideal clocks (clock skew
= 0). Therefore, it is a common practice to give more
constrained timing to placement engine with:
1Extra uncertainty
2Frequency Overdrive
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54. Intro Optimization
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