ppt ISTAMCE 314 conference ppt sample.pptx

conference ppt

1. A Comparitive Performance Analysis of Multi-Gate FinFET Architectures Under PVT Variation Dr. Vikas Mahor Assistant Professor Department of Electronics Engineering Presentation on Paper ID: ISTAMCE 314 MADHAV INSTITUTE OF TECHNOLOGY AND SCIENCE GWALIOR (M.P.)   (A Govt. Aided Autonomous & NAAC Accredited Institute, Affiliated to R. G. P. V. Bhopal)  

2. Contents  Introduction to FinFET Technology .  Introduction to Multi Gate FinFETs .  Parameter variation.  Ring Oscillator design.  Effect of process variation on differenet Multi-Gate FinFETs .  Conclusion. Madhav Institute of Technology & Science

3. C riteria in Choosing a Microcontroller  M eeting the computing needs of the task efficiently and cost effectively speed, the amount of ROM and RAM, the number of I/O ports and timers, size, packaging, power consumption easy to upgrade cost per unit Noise of environment  A vailability of software development tools assemblers, debuggers, C compilers, emulator, simulator, technical support Madhav Institute of Technology & Science

4. Comparison of the 8051 Family Members  ROM type – – – – 8031 n o R OM 80xx m ask R OM 87xx EPR OM 89xx Flash EEPROM  Example (AT89C51,AT89LV51) AT= ATMEL(Manufacture) C = CMOS technology LV= Low Power(3.0v) 89xx 8951 8952 8953 8955 898252 891051 892051 M i cr o co nt ro l l e r Madhav Institute of Technology & Science

5. Comparison some of the 8051 Family Members R OM R AM T im e r 805 1 4 k EROM 1 2 8 2 803 1 - 1 2 8 2 8 9 5 1 4k EPROM 1 2 8 2 805 2 8 k EPROM 25 6 3 803 2 - 25 6 3 8 9 5 2 8k EPROM 25 6 3 Madhav Institute of Technology & Science

6. 8051 Basic Component s  4 K b y t e s i n t e r n a l R O M  12 8 b y t e s i n t e r n a l RA M  Four 8 - b i t I / O po r t s ( P - P 3 ).  T w o 16 - b i t ti mer s / c o u nte r s  On e s e r ial inte rf a c e  64 k e x t e r n a l mem or y f o r c od e  64 k e x t e r n a l mem or y f o r da t a  21 b i t add r es s ab l e Madhav Institute of Technology & Science

7. Block Diagram of 8051 Madhav Institute of Technology & Science

8. 8051 Internal Block Diagram Madhav Institute of Technology & Science

9. 8051 Schematic Pin Diagram Madhav Institute of Technology & Science

10. I mportant P ins (I / O P orts )  Port 0 : pins 32-39 ( P0.0 ～ P0.7 ) 8-bit R/W - General Purpose I/O Or acts as a multiplexed low byte address and data bus for external memory design  One of the most useful features of the 8051 is that it contains four I/O ports (P0 - P3) Each port can be used as input or output (bi-direction) Madhav Institute of Technology & Science

11.  Port 1 （ pins 1-8 ） （ P1.0 ～ P1.7 ） Only 8-bit R/W - General Purpose I/O I mportant P ins (I / O P orts ) Madhav Institute of Technology & Science

12.  Port 2 （ pins 21-28 ) （ P2.0～ P2.7 ） 8-bit R/W - General Purpose I/O Or high byte of the address bus for external memory design I mportant P ins (I / O P orts ) Madhav Institute of Technology & Science

13.  Port 3 ( pins 10-17 ) ( P3.0 ～ P3.7 ) General Purpose I/O Also used for as internal peripherals (timers) or external interrupts. I mportant P ins (I / O P orts ) Madhav Institute of Technology & Science

14. Port 0 with Pull-Up Resistors Madhav Institute of Technology & Science

15. Port 3 Alternate Functions Port Pin Alternate Function P3.0 RXD (serial input port) P3.1 TXD (serial output port) P3.2 INT 0 (external interrupt 0) P3.3 INT 1 (external interrupt 1) P3.4 T0 (Timer 0 external input) P3.5 T1 ( Timer 1 external input) P3.6 WR (external data memory write strobe) P3.7 RD (external data memory read strobe) Madhav Institute of Technology & Science

16. ALE - Address latch enable to select valid address E A / V pp - External access enable EA-0 :execute program in external Memory EA-1 :execute program in internal Memory Vpp : During Flash Programming , this Pin receives 12V Programming Enable Voltage (VPP ). PSEN : Program store enable signal to read e x t e r n a l p r o gr a m mem o r y Other Pins Madhav Institute of Technology & Science

17. Registers D P H DP L P C DP T R P C S o m e 8051 16 -b i t R e g ist e r S o m e 8 -b it R e g i s t e rs of t he 8051 A B R R 1 R 2 R 3 R 4 R 5 R 6 R 7 Madhav Institute of Technology & Science

18. Parallel I/O Ports P o r t 0 l a t c h Por t1 latc h Port 2 latc h Por t3 latc h P o r t P o r t 1 P o r t 2 P o r t 3  Each port can be input or output  Direction is set in Special Function Registers Madhav Institute of Technology & Science

19. Data Pointer ( DPTR )  The data pointer consists of a high byte ( DPH) and a low byte (DPL). It ' s function is to hold a 16 bit address. It may be manipulated as a 16 bit data register or two independent 8 bit register. It serves as a base register in indirect jumps, lookup table instructions and external data transfer. D P H DP L DP T R Madhav Institute of Technology & Science

20. P rogram S tatus W ord (PSW) R S0 R S1 BA N K SELE C TI O N H – 07H B A N K 1 08H – F H B A N K 1 1 1 H – 17H B A N K 2 1 1 18H – 1 F H B A N K 3 C Y A C F R S 1 R S O V P CY = 0 (No Carry) CY = 1 (Carry) AC = 0 (No Auxiliary Carry) CY = 1 (Auxiliary Carry ) OV = 0 (No Overflow) CY = 1 (Overflow) P = 0 (Odd Parity) P = 1 (Even Parity) Madhav Institute of Technology & Science

21. Summary  8051 has 4 8-bit I/O Ports which are used for data and address transfer.  8051 consists of 10 general purpose registers (R0-R7, ACC and Register B).  The Flag register is a SFR used to show the status of arithmetic and logical operations.