presentationofvlsi-180404214525 (2).pptx

VLSI Design related

1. Presentation Outcomes Determination of Pull-Up to Pull-Down Ratio (Z p.u. /Z p.d. ) for an Nmos Inverter driven by another Nmos Inverter. Determination of Pull-Up to Pull-Down Ratio for an Nmos Inverter driven through one or more pass transistor. Transistor Sizing

2. Determination of Pull-Up to Pull-Down Ratio (Z p.u. /Z p.d. ) for an Nmos Inverter driven by another Nmos Inverter. Consider the arrangement in figure 2.8 in which an inverter is driven from the output of another similar inverter. Consider the depletion mode transistor for which V gs = 0 under all conditions, and further assume that in order to cascade inverters without degradation of levels we are aiming to meet the requirement V in = V out = V inv Figure 2,8 Nmos inverter driven directly by another inverter

3. For equal margins around the inverter threshold, we set V inv = 0.5V DD . At this point both transistors are in saturation and I ds = K W (V gs – V t ) 2 L 2 In the depletion mode: I ds = K W p.u. (– V td ) 2 since V gs = 0 L p.u. 2 In the enhancement mode: I ds = K W p.u. (V inv – V td ) 2 since V gs = V inv L p.u. 2 Equating (since currents are the same) we have K W p.u. (V inv – V td ) 2 = K W p.u. (– V td ) 2 L p.u. 2 L p.u. 2

4. Where W p.d. , L p.d. , W p.u. and L p.u. are the widths and lengths of the pull-down and pull-up transistors respectively. Now write Z p.d. = L p.d. W p.d. Z p.u. = L p.u. W p.u. we have 1 (V inv – V t ) 2 = 1 (-V td ) 2 Z p.d. Z p.u. whence V inv = V t - V td (Z p.u. /Z p.d. ) -2 equation (2.9)

5. Now we can substitute typical values as follows: V t = 0.2V DD ; V td = -0.6V DD V inv = 0.5V DD (for equal margins) thus, from equation (2.9) 0.5 = 0.2 + 0.6 (Z p.u. /Z p.d. ) -2 whence (Z p.u. /Z p.d. ) -2 = 2 Squaring on both the sides we get: Z p.u. /Z p.d. = 4/1  Thus, the L:W of (p.u.) Transistor must be in such proportion with respect to another (p.d.) Transistor

6. Determination of Pull-Up to Pull-Down Ratio (Z p.u. /Z p.d. ) for an Nmos Inverter driven through one or more pass transistor

8. Transistor Sizing Transistor sizing is the operation of enlarging (or reducing) the width of the channel of a transistor. It is an effective technique to improve the delay of a CMOS circuit. When the width of the channel is increased, the current drive capability of the transistor increases which reduces the signal rise/fall times at the gate output. The active area, i.e., the area occupied by active devices (e.g., transistors) increases with increased transistor sizes, and the layout area may increase as the complexity of the circuit increases and thus to overcome this transistor sizing is done.

9. Transistor Sizing R ∞ R = R = R ∞ I ∞ (Since, R ∞ 1/I ) R ∞  

10. Some Formulas R eq Series n eq Parallel eq   I eq eq n eq  

11. Example: Find eq and eq where, = 2 and   Pmos Section eq = = 2 + 2 = 4  

12. Example: Find eq and eq where, = 2 and   Nmos Section eq =1/( = 1/ (½+ ½) = ½  

13. Final Sizing eq = 2 eq = ½  

14. Summary Explained basic nmos inverter with its characteristics Explained determination of Pull-Up to Pull-Down Ratio (Z p.u. /Z p.d. ) for an Nmos Inverter driven by another Nmos Inverter. Explained determination of Pull-Up to Pull-Down Ratio for an Nmos Inverter driven through one or more pass transistor. Explained what is transistor sizing with some examples

15. Thank You