printing of ic circuits.pdf

chemistry

1. UNIT V - PLANAR TECHNOLOGY
Semiconducting materials:
These are materials whose conductivity values are between those of
conducting materials and poorly conducting insulators. Elemental
semiconductors are the materials belonging to Group IV of the Periodic
table. Example: Carbon, Silicon, Germanium and Grey Tin. The
semiconducting material used to fabricate devices is a single crystal of
Silicon in the form of circular slices.

Crystal Growth Methods:
Single crystals are obtained by crystallizing from fused
polycrystalline silicon. Polycrystalline silicon is produced from Silica, SiO2
by chemical treatment of sand. Two important methods are used to grow
single crystals of Silicon used in Integrated Circuits. They are Czochralski
process and Float zone process.

Czochralski Process:
This is a process in which a small size single crystal is grown to a
large single crystal. Hence a seed crystal is required for the growth. A
polysilicon melt is prepared by melting Silicon in a Quartz or Graphite
crucible by using rf. The seed crystal is attached to a rotating shaft and the
crystal growth is started by dipping it into the melt. When the bottom of the
seed crystal begins to melt, it is pulled from the melt by slowly rotating and
lifting. The crystal growth starts and Silicon Atoms in the melt crystallize
with single crystal becoming large. The entire setup is enclosed in a
chamber filled with inert gas Argon. This technique is used to grow singe
crystals of many semiconducting materials made of Germanium and
Germanium Arsenide.

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Float Zone Process:
In this process, a rod of pure polycrystalline Silicon is fixed in a
vertical position by means of chucks. It is enclosed in a chamber filled with
inert gas. An rf heater coil is placed around the chamber. A single crystal is
clamped at the lower end of the rod and rotated around its axis. The coil
melts a small length of the rod starting with the seed crystal. The molten
zone is then slowly moved upward along the length of the rod by moving
the rf coil. As it moves up, recrystalllization of the molten zone at the
bottom occurs. A new material begins to melt at the top. The recrystallized
regions assume the crystal structure of the seed.
Float zone process has many advantages over Czochralski process.
 Impurity level in grown crystal is low.
 Oxygen content in Czochralski process is 5x10
17
to 2x10
18
per cubic
cm whereas it is 10
15
per cubic cm in Float Zone process.

Neutron Transmutation Doping:
Single crystals of Silicon grown in any of the above processes may
have radial sensitivity variations. Further, Silicon should be doped with
impurity atoms, such as Phosphorus atoms in case of n-type material. Both
of the purposes are achieved by NTD.
In this technique, Silicon crystal is exposed to the stream of neutrons
of a nuclear reactor. Since, Silicon contains about 3% Silicon isotope
30
Si,
the bombardment causes change of
30
Si to
31
P.

30
Si14 ------->
31
Si14 ------>
31
P15 + β

Thus Phosphorus atoms are introduced into Silicon to form n-type material.
This technique gives uniform doping and also eliminates micro sensitivity
variations.
Wafer Preparation:
The doped semiconductor is of cylindrical shape. It is first subject
to surface grinding which gives a precise cylinder with uniform diameter.
Then by using several slices along the crystal, surface orientation is
determined by X-Ray Diffraction. To the required orientation, then it is cut

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into wafers by using a ring shaped saw blade, with diamond tip. Then
wafers are polished by first mechanical process and then with a chemical
treatment using Alumina and Glycerine, HF, HNO3 and AcOH. Generally,
Silicon wafers used in device fabrication have either a 111 or 100 crystal
orientation.

Methods of P-N Junction Formation:
1. Melt grown junction:
One of the simplest ways to make a P-N junction is the direct
doping of the melt during the growth of the crystal. While preparing single
crystalline Silicon, the impurity is added into the melt so as to introduce the
impure atoms in the rod itself. After the introduction of the one of the type
of the impurity, another type of impurity is added in the melt to introduce
other type. Thus P-type and N-type impurities are introduced to form P-N
junction.
2. Alloying:







In this process, a semiconductor slice is made to contact with an
impurity in a liquid condition at high temperature. A typical example of
this process is P-N junction formation by alloying Ge with In. A small
pellet of in is placed on the surface of n-type Ge. The semiconductor
slot is then placed on a carbon strip heater that is covered with a glass
bell jar filled with an inert gas Ar. When the strip heater is heated to 500
degree Celsius, it melts and dissolves Ge. It forms a small puddle of a
molten In-Ge mixture. When the temperature is lowered, molten mass
starts forming a single
crystal of p-type Ge
doped with In. In the
case of Si, P-N
junction can be made
in a similar way by
alloying Al to n-type
Si.

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3. Solid State Diffusion:
The most widely used technique is Solid State Diffusion.
There are two types. (a) By using open tube furnace. (b) Evacuated sealed
tube in furnace. The former type is the preferred method.

Open Tube Diffusion System:
Here the compound used as a dopand may be a solid, liquid or gas.
The semiconductor samples are placed in a high temperature Quartz tube
furnace. A gas mixture carrying a dopand is made to flow over the samples.
The Quartz tube has an inlet for the gases at one end and is
connected to a vent at the other end. Liquid dopand is converted into
vapour. In the case of Phosphorus diffusion. Ni-Si, POCl3 is used as a
dopand.

4 POCl3 + 3 O2-----> P2O5 + 6 Cl2

P2O5 forms a glass on the Si wafer and is then reduced to P by Si.

5 Si + 2 P2O5 ------> SiO2 + 4 P

The Phosphorus that is released diffuses into the Si and Cl2 leaves through
the vented port.


Ion Implantation:
It is an advantageous technique to introduce dopands. It precisely
controls the amount of dopand and its depth below the surface. It is a low
temperature process to eliminate deformation of wafer.
A beam of ionized atoms is accelerated through a desired potential
(10 to 500 kV). It is made to hit on a semiconductor target. The gas

5. 5

containing atoms of the desired impurity is introduced into a vacuum
chamber. The impure atoms are ionized by collision with high energy
electrons. After collision, in addition to desired ions of impurity atoms,
unwanted species – ions will also be emerging from the chamber. They are
separated by passing the beam through a magnetic field where the desired
ions are deflected to 90
0
. Then the deflected ions are accelerated using an
electric field and made to strike the semiconductor target which is kept at
ground potential. The beam is deflected horizontally and vertically across
the target which gives uniform doping.


Molecular Beam Epitaxy:
It is an evaporation method to obtain a thin layer of P-type or N-
type material. Here the substrate is held in an ultra high vacuum and the
molecular beams are atomic beams of P-type or N-type impurities are made
to impinge on its surface. For example, molecular beam epitaxial growth of
AlGaAs on GaAs substrate is detailed below.
The components Al, Ga ,As and dopands Sn and Be are heated in
separate cells. Each of the cells has a controllable shutter port. Parallel
beams of these substances are directed on to the substrate which is held at a
temperature between 520 and 600
0
C. The striking speed can be precisely
controlled to form uniform growth. Main advantages of this type of doping
are low substrate temperature. High quality films can be grown using this
method.

6. 6

Growth and Deposition of Dielectric Layers:
Dielectric layers are deposited on semiconductor for masking
against diffusion, for electrical insulation for junction passivation and for
mechanical protection of the structure. The most frequently used dielectric
is so
2
.others are Si3N4 and polysilicon.SiO2 can be deposited by thermal
oxidation of silicon.

Thermal Oxidation of Silicon:
Dry silicon wafers are loaded with open ended quartz tube
which is kept in electric furnace maintained at temperature 900 to 1200
0
C.
High purity oxygen is passed through high pure water just below its boiling
point. The O2 saturated with water vapour oxidizes the Si surface.

Si +O2--->SiO2
Si+2H2O--->SiO2+2H2

Chemical Vapour Deposition (CVD):
This technique is normally employed for substrates other
than Si. It involves the flow of a gas with diffused reactants over hot silicon
wafer. For the preparation of silicon dioxide layers, SiH4 and O2 are
reactants used between 250 to 500
0
C
SiH4 +2O2--->SiO2+2H2O

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A gas mixture containing either N2 or Ar with O2 and about 1% SiH4 is
used. The SiO2 growth rate depends on the substrate temperature and the
rate of gas flow. The gas that carries the reactants is called the carrier gas.
In the reactors, the silicon surface is exposed to the flowing gas with
diffused reactants.
Sputtering:
Sputtering is a process in which energetic ions knock atoms or
molecules from a target that acts as one electrode. This is subsequently
deposited on a silicon wafer that is acting as an another electrode.
Here SiO2 block is made the cathode, and the silicon waters are placed
on the anode which is kept at ground potential. An rf voltage at about 10
MAZ is applied between the cathode and anode. As argon is passed, they
become ionized Ar ions bombard cathode and electrons flow to the SiO2
cathode, which then becomes negatively charged.SiO2 is deposited on
substrate.

Planar technology:
A majority of silicon devices are fabricated using planar process.
Since the device fabrication process is carried out from one surface plane, it
is called planar technology.
In this process dopand atoms are introduced into selected areas of
Si from one n–and p-type regions in the starting material .

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A majority of silicon devices are fabricated using the planar process:

1, A thin layer of Si is grown on the ‘n’ substrate.
2, Wafer is cleaned and SiO2 layer is coated by thermal oxidation.
3, The top surface of the wafer is then coated with photosensitive material.
4, The area of the P-N junction formation is fixed by keeping a mask over
wafer.
5, A mask is a glass plate over which a drawing of circuit is printed.
6, U-V light is exposed on the plate.
7, The photosensitive monomer is polymerized whenever light is fallen.
8, Then glass plate is removed and unpolymerised area is washed away.
9, Then wafer is etched using HF to remove SiO2 layer followed by
washing with solvent to remove polymerized layer.
10, P-region is produced by boron diffusion.
11, A thin aluminium layer is deposited and similar procedure of masking
and etching of metal is done, to have electrical contact.
Thus N-P junction is formed over silicon wafer.

Masking and Lithography
Production of Mask:
Using computer controlled drawing boards, mask making is done by
micro processors. The drawings are photographically reduced to appropriate
size. Then they are transferred to a glass plate, called master. This is used
for taking more copies on photographic glass plates.
An alternate method is drawing of circuits using computer controlled
light flashes or a light pencil on a photographic plate.
Photo-Lithography:
This process involves transfer of circuit image from the mask to the
surface of wafer. Photosensitive monomer or photoresist are chemical
compositions containing a light sensitive material in suspension. This
material responds to UV light.

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The silicon wafer is coated with photoresist using spin coating. The
wafer is placed on a flate holder on the top of a rotating shaft. The wafer is
held by vacuum inside the holder. The shaft is then rotated. As the wafer
spins, to resist spreads uniformly over the wafer’s surface. After coating is
done, the wafer is removed and baked in an oven to remove solvent.
Electron beam Lithography:
This is based on the production of circuit pattern on silicon by means of
electrons. The electron beam is produced by a photo cathode when it is
irradiated by UV² light. These electrons are accelerated by electric field
between the mask and the semiconductor wafer. These are then focused on
the photoresist. High image resolution is an advantage of this system.
Etching:
Etching is done for the removal of dielectric layer, SiO2 and the
removal of metal layers. There are many types of etching:
1. Wet etching:
This is done by immersing the wafer into a solution mixture of HF +
NH4F to remove SiO2 layer at a constant temperature. In metal etching Al
is etched by H3PO4 or HNO3 or acetic acid. The drawback of this etching is
undercutting (not properly removing), dissolving of photoresist and
unwanted etching at the corners.
2. Electrochemical etching:
A voltage is applied between the etchant and material to be etched, to
a controlled removal.
3. Sputter etching:
Sputtering is the removal of material by un bombardment. The
material to be etched is made cathode and Ar ions are used. Since the ions
impinge the surface nearly vertically, no undercutting occurs. After cooling
to room temperature, the wafer is exposed to UV light through an
appropriate mask. The area whenever light has fallen, is polymerized and
got hardened. The hardened area will been insoluble in developer(solvent)
whereas unexposed area will become soluble and be dissolved. In order to
have accurate formation of circuit over silicon wafer, the mask should be
kept so close to silicon wafer by a distance of about 20μm.
4. Plasma etching:
It is a dry chemical etching technique. Here some reactive gases such as
CF4, CCl4 are used for etching Si or SiO2. After filling the reactor with the
reactive gas the plasma is produced by an rf field. The plasma of reactive
gas, react with the material to be etched and form volatile that are exhausted
from the reactor.
Advantage: Less undercutting.