Processor Design Flow for architecture design

Lecture Notes

1. Module III:

Processor Design Flow and Memory :
Processor Design Flow :
Capturing requirements, Instruction coding, Exploration
of architecture organizations, hardware and software
development. Extreme CISC and extreme RISC, Very long
instruction word (VLIW).
Memory : Organization, Memory segmentation,
Multithreading, Symmetric multiprocessing.

2. Module III: A: Processor
Design flow

3. Hardware and software development
•The hardware development follows typically the
normal ASIC or FPGA design flow, including
high-level modeling, refinement of functional
blocks in a hardware description language such
as VHDL or Verilog, logic synthesis,
floorplanning, back-end optimizations and
verifications using simulators and static analysis
tools.

4. 4
VLSI Design Flow
ENTITY test is
port a: in bit;
end ENTITY test;
DRC
LVS
ERC
Circuit Design
Functional Design
and Logic Design
Physical Design
Physical Verification
and Signoff
Fabrication
System Specification
Architectural Design
Chip
Packaging and Testing
Chip Planning
Placement
Signal Routing
Partitioning
Timing Closure
Clock Tree Synthesis
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5. ASIC Design Flow
•ASIC tools are generally driven
by scripts
•Post-synthesis static timing
analysis and equivalency
checking are musts for sign off
to foundry
•Verification of deep sub-micron
effects (second- and third-
order effects) is required for
ASICs
▫Internal, deep sub-micron
effects are already verified
for Xilinx FPGAs

6. FPGA Design Flow
•FPGA tools are generally
GUI-driven, pushbutton flows
▫FPGA tools also have scripting
capabilities
•After the design passes behavioral
simulation and static timing
analysis, verification is completed
most efficiently by verifying in
circuit
▫Fast turnaround times
▫Static timing analysis is used to
verify timing of the design
▫Timing simulation is supported
▫This is a simplified/typical design
flow

7. ASIC Implementation
•Create HDL
▫Optimized for ASIC
technology and area
•Synthesis
▫Primarily driven by scripts
▫Synopsys design compile
▫Design for test logic insertion
(BIST, Scan, and JTAG)
•Place & route
▫Foundry tools, Cadence,
AVANT

8. FPGA Implementation
•Create HDL
▫Optimized for Xilinx FPGAs and
performance
•Synthesis
▫Synopsys, Mentor, XST
▫Pushbutton flow with
scripting capabilities
•Place & route
▫Completed by the user
▫Xilinx implementation tools – ISE®
software
▫Pushbutton flow, scripting capabilities

9. Software Development flow
•Waterfall Model
•V Model
•Spiral Model

10. Waterfall Model
•Requirements – defines
needed information, function,
behavior, performance and
interfaces.
•Design – data structures,
software architecture, interface
representations, algorithmic
details.
•Implementation – source
code, database, user
documentation, testing.

11. V-Shaped SDLC Model

12. Spiral SDLC Model

13. Software tools and libraries
•The SW tools and utilities that are necessary
typically include
▫Assembler
▫Linker
▫Instruction Set Simulator (ISS) which typically
integrates also a debugger
▫High-level language compiler (e.g., C/C++)
▫Real-time operating system (RTOS) in more
complex systems
▫Application examples and libraries