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1. SAINTGITS COLLEGE OF ENGINEERING (AUTONOMOUS) LEARN . GROW . EXCEL Implementation Of 32-bit RISC Processor Using Vedic Mathematics

2. SAINTGITS COLLEGE OF ENGINEERING (AUTONOMOUS) LEARN . GROW . EXCEL Project Area : VLSI Project Topic : Implementation of 32-bit RISC Processor using Vedic Mathematics Supervisor Name: Er. Anish M George Designation: Assistant Professor Presented by: Navaneetha A Nair (MGP19EC036) P S Sreeya (MGP19EC038) Ribin K Thomas (MGP19EC040) Vijay R (MGP19EC053) S8 ECE Saintgits College of Engineering

3. LEARN . GROW . EXCEL Contents Motivation Literature Survey Objectives Modules & Tools Block Diagram Of 32-bit Risc Processor Vedic Sutra Results Comparison of 32-Bit Vedic Multiplier and 32-Bit Array Multiplier Conference Presentation Conclusion References

4. LEARN . GROW . EXCEL Motivation Unsatisfactory or dire performance of existing 16-bit processor. 16-bit processor is unable to handle graphics and large data structures. 32-bit processor is able to handle graphics and large data structures. A 32-bit processor can be also implemented by cascading two 16-bit processors, but it is slow and address computation becomes too complex. Conventional 32-bit processor lacks space complexity and power consumption. Vedic Mathematics ancient method of mathematical computation enhances the performance of 32-bit processor.

5. LEARN . GROW . EXCEL Literature Review Sl. No Title Authors & Publications Techniques Used and Observations 1 Design and Verification of 16-bit RISC processor using Vedic Mathematics. Yadav,Ankitha and Varsha Bendre. International Conference on Smart Computing and Informatics(ESCI). IEEE,2021. Techniques :A 16-bit RISC Processor is designed using Verilog Hardware Descriptive Language and is stimulated using Xilinx ISE.Multiplier unit in ALU and MAC is designed using Vedic Sutras. Observations: There is 44% savings in power in case of MAC and that of 12% in case of ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced by 45% in case of MAC and that of 35% in case of ALU in comparison with conventional ALU and MAC correspondingly.Hence improvement in speed of operation,reduced power consumption and area are the main features of the designed processor.

6. LEARN . GROW . EXCEL Sl.No Title Authors & Publications Techniques Used and Observations 2 Implement 32-bit RISC-V Architecture Processor using Verilog HDL . Lai, Jin-Yang, et al. "Implement 32-bit RISC-V Architecture Processor using Verilog HDL." 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS). IEEE, 2021. Techniques: A 32 bit RISC-V processor is designed using verilog that supports RV32I and Modelsim is used to verify it. Observations: ModelSim is used to simulate a RISC-V processor that can use Verilog to execute 13 instructions in RV32I, it is confirmed that it can work normally. Literature Review…contd

7. 3 Realisation of Vedic Sutras for Multiplication in Verilog. Kamaraj, A., A. Daisy Parimalah, and V. Priyadharshini. "Realisation of Vedic Sutras for Multiplication in Verilog." SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) 4.1: 25-29. Techniques : 8*8 bit VM using “Urdhva Tiryakbhyam” Sutra , “Ekanyunena Purvena” Sutra , “Anurupyena ” Sutra and “Antyayor Dasakepi” Sutra and is implemented in Verilog. Simulation was done using modelsim and Logic synthesis was observed using ISE Design suite and implemented in Xilinx Spartan 6. Observations : The computational path delay of Vedic multiplier is found to be 17.59ns. Hence the proposed VM seems to be highly efficient in terms of speed .Reducing time delay is very essential requirement for many applications and VM technique is very much suitable for this purpose. Literature Review…contd Sl. No Title Authors & Publications Techniques Used and Observations LEARN . GROW . EXCEL

8. LEARN . GROW . EXCEL Literature Review…contd 4 Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques. Kumar, G. Ganesh, and V. Charishma. "Design of high speed vedic multiplier using vedic mathematics techniques." International Journal of Scientific and Research Publications 2.3 (2012): 1. Techniques : The Verilog HDL coding of Urdhva tiryakbhyam Sutra for 32x32 bits multiplication and their FPGA implementation by Xilinx synthesis Tool on Spartan 3E kit have been done and output has been displayed on Spartan 3E kit. Observations : The computation time for calculating the product is 31.5296ns. VM are much faster than conventional multipliers which gives the method for hierarchical multiplier design so the design complexity gets reduced for inputs of large number of bits and modularity gets increased. Exhibits improved efficiency in terms of speed. Sl. No Title Authors & Publications Techniques Used and Observations

9. LEARN . GROW . EXCEL Objectives To advance the characteristics and application of 32-bit processor compared to 16 bit processor. To increase the efficiency and accuracy of existing 32 bit RISC processor. To apply Vedic sutras in ALU design for speed calculation. To reduce the drawbacks of 32 bit processor such as critical path delay and power consumption. To improve the quality and enhance the usage of 32 bit processor in existing as well as future applications.

10. LEARN . GROW . EXCEL Tools Modules ALU Mux 2 X 1 Control Unit Buffer Register Program Counter Register File Xilinx Vivado 18.3

11. LEARN . GROW . EXCEL Block Diagram of 32-Bit RISC Processor Fig 1 :Block Diagram of Risc Processor

12. LEARN . GROW . EXCEL Vedic Sutra Consist of 16 sutras Efficient Sutra - Urdhva Tiryakbhyam Sutra. Meaning : vertically and crosswise. Example: Multiply 743 by 651.

13. LEARN . GROW . EXCEL Results : ALU In the design of ALU,we have used Vivado 18.3 for the synthesis and simulation.We have given 32-bit inputs a,b and 6-bit opcode i.e alufn.We obtained the output otp and an overflow depending on the arithmetic and logical operations performed. The Synthesis and Simulation Results of the ALU are given in the Figure . Fig 2 : Synthesis and Simulation results of ALU

14. 32-bit CPU In the design of CPU we have the inputs as “a” ,”b” and ALU instruction code “alufn”.We have simulated and synthesized the block using vivado 18.3 and obtained the output otp. Fig 7 : Synthesis and Simulation result of CPU

15. LEARN . GROW . EXCEL Vedic Multiplier Fig 8 :32-Bit Vedic Multiplier Simulation Fig 9 :32-Bit Vedic Multiplier RTL

16. LEARN . GROW . EXCEL Array Multiplier Fig 10 : 32-Bit Array Multiplier Simulation Fig 11 :32-Bit Array Multiplier RTL

17. LEARN . GROW . EXCEL Comparison of 32-Bit Vedic Multiplier and 32-Bit Array Multiplier Timing Report : 32- Bit Vedic Multiplier Timing Report : 32-Bit Array Multiplier

18. LEARN . GROW . EXCEL Comparison of 32-Bit Vedic Multiplier and 32-Bit Array Multiplier LUT Report : 32- Bit Vedic Multiplier LUT Report : 32-Bit Array Multiplier

19. LEARN . GROW . EXCEL Comparison of 32-Bit Vedic Multiplier and 32-Bit Array Multiplier Power Dissipation Report : 32- Bit Vedic Multiplier Power Dissipation Report : 32-Bit Array Multiplier

20. LEARN . GROW . EXCEL Comparison of 32-Bit Vedic Multiplier and 32-Bit Array Multiplier Major improvement in performance characteristics 97% reduction in LUT units 17.15% reduction on chip power 21.05% improvement in critical path delay Positive impact on size, power and speed

21. Conference Presentation The paper titled, “32-bit RISC Processor Using Vedic Mathematics” has been selected and presented in the National Conference on Research in Emerging Areas (NACORE 23) co-sponsored by KSCSTE and ACM Kottayam Chapter held at Amal Jyothi College of Engineering, Kanjirapally on 26th and 27th April 2023.

22. References Yadav, A. an ed Bndre, V , 2021, March. “Design and Verification of 16-bit RISC Processor Using Vedic Mathematics”. In 2021 International Conference on Emerging Smart Computing and Informatics (ESCI) (pp. 759-764). IEEE. Kamaraj, A., Parimalah, A.D. and Priyadharshini, V. , “Realisation of Vedic Sutras for Multiplication in Verilog” . SSRG International Journal of VLSI & Signal Processing (SSRG-IJVSP) . Lai, J.Y., Chen, C.A., Chen, S.L. and Su, C.Y ., 2021, November. “Implement 32-bit RISC-V Architecture Processor using Verilog HDL”. In 2021 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) (pp.IEEE. Kumar, G.G. and Charishma, V. , 2012. “Design of high speed vedic multiplier using vedic mathematics techniques”. International Journal of Scientific and Research Publications . Gadda, Nilam, and U. Eranna . "64-bit ALU design using vedic mathematics." 2020 international conference on emerging trends in information technology and engineering IEEE, 2020.

23. References Galani Tina, G., Riya Saini, and R. D. Daruwala. "Design and Implementation of 32-bit RISC Processor using Xilinx." International Journal of Emerging Trends in Electrical and Electronics 5.1 (2013). Bisoyi, Abhyarthana, Mitu Baral, and Manoja Kumar Senapati. "Comparison of a 32-bit Vedic multiplier with a conventional binary multiplier." International Conference on Advanced Communications, Control and Computing Technologies. IEEE, 2014. Lad, Shraddha, and Varsha S. Bendre. "Design and comparison of multiplier using vedic sutras." 2019 5th International Conference On Computing, Communication, Control And Automation (ICCUBEA) . IEEE, 2019. Bansal, Yogita, Charu Madhu, and Pardeep Kaur . "High speed vedic multiplier designs-A review." 2014 Recent Advances in Engineering and Computational Sciences (RAECS) (2014).

24. LEARN . GROW . EXCEL THANK YOU