Project report : trafficlights

project on traffic lights

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PROJECT REPORT:

PROJECT:

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Circuit diagram & elements ………………………………………………………………………………… 3
Project theory ………………………………………………………………………………… 4
Description about IC4017 ………………………………………………………………………………… 4
Features & applications …………………………………………………………….. 5
Logic diagram of IC4017 ……………………………………………………… …….. 7
Characteristics of IC4017 ……………………………………………………………… 8 -10
Features & application ……………………………………………………………… 11
of 555 timer
Characteristics of 555 timer ………………………………………………………........ 12
Circuit design on ISIS ……………………………………………………………… 13 -14
Circuit design on ARES ………………………………………………………………………………… 15
3D vision of PCB Chip ………………………………………………………………………………… 16
Circuit design on bread board ………………………………………………………………………….. 17
Print preview of ARES design …………………………………………………………………………… 17
Complete view ………………………………………………………………………………… 18
References …………………………………………………………….. 19

For help and further info :
[email protected]
facebook.com\zainali

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 IC CD4017
 555 TIMER
 DIODE IN4007 x 6
 CAPACITORS ( 10µf,1µf (2) )



CIRCUIT DIAGRAM:













CIRCUIT ELEMENTS:

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 RESISTORS 1) 100 KΏ 2) 22 KΏ 3) 220 KΏ x
3
 LED 1) GREEN x 4 2) RED x 4
3) YELLOW x 4
 POTENTIOMETER
 BATTERY 9V



This Traffic control circuit
can be used to control traffic on roads or in public places. In one
traffic signal there are three led of different color. RED, YELLOW and
GREEN are used in a traffic signal. This circuit used 555 timer as
multivibrator for rapid squire wave pulse generation. This clock pulse is
feed to IC4017. IC4017 is a counter IC. In this counter IC for every
pulse fed to input pin-14, the high level output keep shifting from D1 to
D9 in cyclic order.
At a time one output is higher and other output pins are on low state.


General Description:
The CD4017 is a 5-stage divide-by-10 Johnson counter with 10 decoded
outputs and a carry out bit. This counter is cleared to its zero count by
a logical “1” on their reset line. This counter is advanced on the
positive edge of the clock signal when the clock enable signal is in the
logical “0” state. The configuration of the CD4017 permits medium speed
operation and assures a hazard free counting sequence. The 10 decoded
outputs are normally in the logical “0” state and go to the logical
“1” state only at their respective time slot. Each decoded output
remains high for 1 full clock cycle. The carry out signal completes a
full cycle for every 10 clock input cycles and is used as a
ripple carry signal to any succeeding stages.
Features:

PROJECT THEORY:

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 Wide supply voltage range: 3.0V to 15V
 High noise immunity: 0.45 V DD (typ.)
 Low power Fan out of 2 driving 74L TTL compatibility: or 1 driving
74LS
 Medium speed operation: 5.0 MHz (typ.) with 10V V DD
 Low power: 10 µW (typ.)
 Fully static operation
Applications:
 Automotive
 Instrumentation
 Medical electronics
 Alarm systems
 Industrial electronics
 Remote metering
ORDERING CODE:
Order Number Package
Number
Package Description
CD4017BCM M16A 16-Lead Small Outline Integrated Circuit
(SOIC), JEDEC MS-012, 0.150” Narrow
CD4017BCSJ M16D 16-Lead Small Outline Package (SOP), EIAJ
TYPE II, 5.3mm Wide
CD4017BCN N16E 16-Lead Plastic Dual-In-Line Package (PDIP),
JEDEC MS-001, 0.300” Wide
CD4022BCM M16A 16-Lead Small Outline Integrated Circuit
(SOIC), JEDEC MS-012, 0.150” Narrow
CD4022BCN N16E 16-Lead Plastic Dual-In-Line Package
(PDIP), JEDEC MS-001, 0.300” Wide


PIN Assingnment IC 4017B:

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LOGIC DIAGRAM

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DATA SHEET OF 555 TIMER:

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DESCRIPTION:
The LM555/NE555/SA555 is a highly stable controller capable of producing
accurate timing pulses. With monostable operation, the time delay is
controlled by one external resistor and one capacitor. With astable
operation, the frequency and duty cycle are accurately controlled with two
external resistors and one capacitor.
FEATURES:
• High Current Drive Capability (200mA) • Adjustable
Duty Cycle
• Temperature Stability of 0.005%/°C • Timing
From µSec to Hours
• Turn off Time Less than 2µSec
APPLICATIONS:
• Precision Timing
• Pulse Generation
• Time Delay Generation
• Sequential Timing

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INTERNAL BLOCK DIAGRAM

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CIRCUIT DESIGN ON ISIS:



PROJRCT WORK ON PROTEUS:

This image is taken after designing circuit diagram of traffic lights on Proteus.
This image is taken when one red led of 1
st
signal and one green led of 2
nd
signal

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This image is taken when yellow led of both signals glow.


This image is taken when green led of 1
st
signal and red led of 2
nd
signal glow.

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CIRCUIT DESIGN ON ARES:

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3D VISION OF CHIP ON ARES:

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PROJECT WORK ON HARDWARE


LAYOUT OF ARES DESIGN:


CIRCUIT DESIGN ON BREAD BOARD:

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REFRENCES:
 WWW.CIRCUITEASY.COM
 WWW.ELECTRONICSHUB.ORG
 WWW.DIGITALCOMMONS.COM
 WWW.ENGINEERSGRAGE.COM
 WWW.TECHNOLOGYSTUDENT.COM
 WWW.ELECTROSCHEMATICS.COM
 WWW.ALLDATASHEET.COM