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1. BANGALORE INSTITUTE OF TECHNOLOGY Department of Electronics and Communication Engineering f or the subject DIGITAL VLSI DESIGN (22LVS14) A Review on Implementation of Boolean and Arithmetic Functions with 8T SRAM Cell for In-Memory Computation Under the guidance of : Dr. A B kalpana Mam Professor, Dept. of ECE, BIT, Bangalore. Presented by : MOHAMMED RAHID VLSI Design & Embedded Systems BIT, Bangalore.

2. ABSTRACT In-memory computational methodology and arithmetic circuit co- designs using 8T SRAM cell. The Boolean logic operation and arithmetic functions are demonstrated with 8T SRAM cell in 180 nm CMOS technology . The NAND, AND, NOR, OR Boolean logics are demonstrate using 8T SRAM cells with the proposed sensing scheme to verifying the In-Memory computations ability of 8T SRAM cells. This proposed sensing scheme with 8T SRAM cell provides an energy improvement of 26.4% over 8+T SRAM based IMC and also offer a high sense margin of NAND and NOR operation.

3. INTRODUCTION The current computing system based on von-Neumann architecture is facing a memory wall, power wall, in- struction parallelism wall. These walls of the current computing system have been a significant impact on computing efficiency of computing systems in the present time due to high prominence on Data insensitive applications . Conventional von-Neumann architecture has a separate unit for storage and computation, as shown in Below fig 1(a ).

4. This physically separated memory and computation unit result in large energy consumption for data transfer between these two units . Fig. 1. a) The Von-Neumann architecture based computing system.

5. There have been many attempts for evaluation in a computing system to overcome these three walls. To suppress these wall and to minimizing the energy consumption, computation-In-Memory ( CIM) architecture has been recently used in a computing system, where data process inside the memory array, as shown in Figure 1(b). This structure will saved the energy which consume for data transfer between memory and ALU unit . b)The In-Memory computing based computing system .

6. CIRCUIT DIAGRAM. Fig. 2. a) The schematic of 8T SRAM Cell. b) The circuit schematic of IMC operation With 8T SRAM Cell and Sense amplifier.

7. The In-Memory computation(IMC) [3] means that data processing operations such as computation, movement, and storage of data are operated inside memory array. The principal purpose behind 8T SRAM cell-based IMC is to enable multiple read word lines simultaneously in 8T SRAM array , which leads the multiple RBL connected to sense amplifier . This 8T SRAM bit-cell consists of the 6T cell to write the data and two additional transistor N5-N6 use for read port, which is shown in Figure 2(a). Due to this configuration , there is possible to get a Boolean logic operation through this cell. In order to realize boolean logic gates operation, the two different cells were shown in Figure 2(b ) to store the two operands and get logic gates output through a sense amplifier, which senses the change on RBL voltage.

8. Figure 2(b) has shown the IMC operation trough 8T SRAM by enabling two read word line simultaneously and VRBL and VRef voltage connected to sense amplifier, here we use latch type sense amplifier [10] with 300 fF RBl capacitor value . The RBL voltage VRBL is initially precharged to VDD , which discharge or at precharged state according to the data store in bit-cell. We propose a sensing scheme to identified the different values of VRBL and thereby compute logic operation of store operand value in bit- cell.

9. Fig. 3. Sensing scheme for IMC operation. a)Sensing scheme for OR/NOR operation. b) Sensing scheme for AND/NAND operation. c)The reference voltage range in sensing scheme I mplementation Of Boolean Function

10. Fig. 4. Simulation in SPICE for IMC operation: a) The output for all possible input(00,01,10,11) for performing NOR/OR operation. b) The output for all possible input(00,01,10,11)for performing NAND/AND operation

11. In order to realize NOR and OR operation through 8T SRAM cell, we use the sensing scheme as shown in Figure 3(a ), where V RBL is connected to the positive terminal of a sense amplifier and reference voltage V Ref −NOR is connected to the negative terminal . We choose the VRef −NOR value in between VRBL (01 / 10) and VRBL (11),which is near to VDD value , as shown in Figure 3(c). As a result, among the possible value of VRBL (see figure 4) with different value stores into a cell, Only VRBL (00) is higher than VREF − NOR . As a result of sensing scheme , when both bit-cell store ”0 ”,which leads the sense amplifier output to logic ”0” at positive and logic ”1” at negative terminal, while all other case leads the sense amplifier output to logic ”1” at positive and logic ”0” at negative terminal. 1. Bit-wise NOR/OR operation:

12. 2. Bit-wise NAND/AND operation: In order to realize a bit-Wise NAND and AND Boolean logic operation through 8T SRAM cell. We use the sensing scheme as shown in figure 3(b), where VRBL is connected to positive terminal of sense amplifier(SA) and reference voltage VRef −NAND is connected to negative terminal of SA. We choose the VRef −NAND value in between VRBL (01 / 10) and VRBL (00 ), as shown in Figure 3(c). The positive and negative terminal of sense amplifier replicates AND and NAND operation of stored value in the bit-cell, when SEN at high condition , which we can be seen in the timing diagram of NAND/AND operation, as shown in Figure 4(b). The timing diagram , as shown in Figure 4(b), consists of all input conditions and the corresponding output of NAND/AND operation .

13. Arithmetic circuit Implementation The 8T SRAM Cell array contains a Pre-charging circuit sensing circuit, and SRAM bit-cell. In this array, we use the NMOS transistor as a pre-charging circuit, and latches type sense amplifier as a sensing circuit, which is shown in Figure 5. We serially mapped the NOR netlist into memory array to demonstrate the functionality of arithmetic circuits. Here we implemented and demonstrate the half adder and Half subtractor circuit operation using 8T SRAM bit-cell and proposed sensing scheme based

14. Fig. 5. a) NOR netlist of Half adder. b ) The mapping of half adder NOR netlist into SRAM array. Fig. 6. a)The SUM and CARRY output for two input condition- 01and10 b)The SUM and CARRY output for two input condition-11 and 00 A. Half Adder

15. Fig. 7. a) NOR netlist of Half Subtractor . b ) The mapping of half subtractor NOR netlist into SRAM array. Fig. 8. a) The Difference and Borrow output for two input condition 01and10 b) The Difference and Borrow output for two input condition-11and00. B. Half Subtractor

16. CONCLUSION In this paper, we present an In-memory computational methodology and arithmetic circuit co-design using 8T SRAM cells with the proposed sensing scheme. The proposed sens - ing scheme provides higher robust operation for NAND and NOR operation for 8T SRAM based IMC. The 8T SRAM shows a high read margin and also energy efficiency for reading and write operation along with the demonstration of energy-efficient In-Memory computation operation using the proposed sensing scheme. Our result is obtained by rigorous spice simulation perform using 180nm CMOS library. The arithmetic circuit also demonstrates in SRAM array using 8T SRAM bit-cell to see the feasibility of computation inside the SRAM memory array.