Ring Counter.pptx

This PPT explains circuit and working of Ring counter

1. Ring Counter III PHYSICS – 08.04.2022 Dr.R.Hepzi Pramila Devamani, Assistant Professor of Physics, V.V.Vanniaperumal College for Women, Virudhunagar.

2. Ring Counter In a ring counter, the true output Q of the last flip flop in a shift register is connected back to the serial input of the first flip flop and also only one flip flop is set at any particular time while all others are cleared. The flip flops are connected in such a way that information shifts either from left to right and back around from Q D to Q A or from right to left and back around from Q A to Q D. Since a single 1 in the register is made to circulate around th register as long as clock pulses are applied, it is called a ring counter.

3. Ring Counter A 4-bit ring counter using D flip flops is shown in Fig. This circuit consists of four D flipflops and their outputs are Q A, Q B, Q C and Q D respectively. The PRESET input of first flip flop and clear inputs of other three flip flops are connected together and brought out as INIT input. On applying a LOW pulse at this INIT input, the first flip flop is SET to 1 and the other three flip flops are cleared to 0, i.e. Q A Q B Q C Q D = 1000.

4. Ring Counter From this circuit it is clear that D A = 0, D B = , D C = , and D D = 0. When the clock pulse is applied, the second flip flop is set to 1 while the other three flip flops are reset to zero. i.e. the output of the ring counter is Q A Q B Q C Q D = 0100. On the occurrence of the first clock pulse, the 1 in the first flip flop is shifted to the second flip flop. Similarly, when the second clock pulse is applied, the 1 in the second flip flop is shifted to the third flip flop and the ring counter output Q A Q B Q C Q D = 0010. On the occurrence of the fourth clock pulse, the output will be Q A Q B Q C Q D = 0001.

5. Ring Counter On the fifth clock pulse Q A Q B Q C Q D = 1000, i.e. the initial state. Thus, 1 is shifted or circulated around the register as long as clock pulses are applied. The truth table which describes the operation of 4- bit ring counter s shown.

6. Ring Counter As in the truth table, the ring counter has only 4 valid states i.e. 1000, 0100,0010,0001. The ring counter can hang or enter into any one of the invalid state due to noise or any other condition without returning to the main counting sequence. Hence it is a must to design ring counters which are self correcting and capable of recovering from invalid states to valid states.

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