RISC - Reduced Instruction Set Computing

A detailed presentation about what is RISC and some of the basic differences between RISC and CISC Computers.
Also enlisting some of the major applications of RISC in the field of Technology.

1. MEMBERS Tushar Swami Vikas Prasad Tanish Garg Anurag Aggarwal

2. OUTLINE What is RISC? CISC Background and History Characteristics Pipelining Hardware RISC v/s CISC Performance Equation Applications of RISC RISC & CISC Convergence

3. ACKNOWLEDGEMENT We would like to express our special thanks of gratitude to our teacher Dr . Praveen Kant Pandey who gave us the golden opportunity to present this wonderful presentation on the topic RISC , which also helped us in doing a lot of Research and we came to know about new things. We are really thankful to her.

4. WHAT IS RISC???

5. INTRODUCTION RISC – Reduced Instruction Set Computer RISC is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions rather than a more specialized set of instructions. The main alternative for RISC is CISC ,which stands for complex instruction set computer. CISC is the older approach, that came about to maximize performance of earlier computer’s. Where instructions were executed sequentially. The instruction set is the hardware language that tells the processor what to do. Sources : http ://search400.techtarget.com/definition/RISC

6. BACKGROUND AND HISTORY RISC approach developed as a result of development in 1970’s - increase in memory size - decrease in cost - advanced compilers In late 1970’s IBM was the first to start. In 1980 , D avid P atterson ,began the project that gives this approach RISC. After some years , S tanford MIPS was developed. Sources : http ://search400.techtarget.com/definition/RISC

7. CHARACTERSTICS OF RISC Simplified instructions , taking 1 clock cycle. Large no. of general purpose registers . Circuit is much simpler . Fast to decode. Fast to execute. Pipelining- fetching of next instruction while previous instruction executes. Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/whatis/index.html

8. PIPELINING Pipelining , a standard feature in RISC processors, is much like an assembly line. A useful method of demonstrating this is the laundry analogy.   Let's say that there are four loads of dirty laundry that need to be washed, dried, and folded.  Washer - 30 minutes Dry - 40 minutes Folding - 20 minutes Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html

9. Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html

10. Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html

11. RISC PIPELINES A RISC processor pipeline operates in much the same way, although the stages in the pipeline are different fetch instructions from memory read registers and decode the instruction execute the instruction or calculate an address access an operand in data memory write the result into a register Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html

12. T he length of the pipeline is dependent on the length of the longest step.  Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/pipelining/index.html

13. HARDARE UTILIZATION For any given level of general performance, a RISC chip will typically have far fewer transistors dedicated to the core logic which originally allowed designers to increase the size of the register set . RISC designs are also more likely planning to feature a Harvard memory model , where the instruction stream and the data stream are conceptually separated. Sources : https://www.youtube.com/watch?v=mDrUkjOVtAU

14. CISC vs. RISC

15. CISC Complex Instructions. ADD AX,[ BX + SI + 600H ] Many operations in single instruction. RISC Simpler or reduced instructions. LOAD R1, addresss1 LOAD R2, address2 ADD R1, R2 STORE address1, R1 One instruction one operation. INSTRUCTION Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/

16. CISC RISC CODE SIZE Code size is larger but simpler. Code size is smaller but complicated. Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/

17. CISC Fewer register . These registers are designed for special purposes. CISC designs provide a large number of addressing modes. RISC Large number of registers . Here registers are identical so any register can be used for any purpose. RISC designs have single addressing modes. REGISTERS AND ADDRESSING MODE Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/

18. CISC Slower to execute. Difficult to decode . Instruction size varies in different instructions . Complex circuit design. RISC Faster execution. Easy to decode. Same i nstruction size in every instructions. Circuit design is simpler. Sources : http://techupdates.in/difference-between-risc-and-cisc-processor-architectures/

19. RISC APPLICATIONS

20. Low end & mobile system ARM ARCHITECTURE Android based systems/ Apple iPhone/ Nintendo GBA etc. MIPS line in PlayStations, Nintendo 64 etc. Atmel AVR Xbox handheld controllers to BMW cars High end risc & supercomputing MIPS used in embedded system in routers, used by   Digital Equipment Corporation etc. IBM’S Power Architecture In many IBM’s supercomputers, workstations etc. Alpha In Single-board computers, Servers & Supercomputers from Digital Equivalent Cooperation etc. RISC APPLICATIONS Sources : http://embeddedcraft.org /

21. ARM Architecture Developed by Advanced RISC Machines (ARM ). ARM makes 32-bit & 64-bit RISC multi-core processors. Features of ARM architecture : A  load/store  architecture An  orthogonal  instruction set. Fixed instruction width  Mostly single clock-cycle execution. Enhanced power-saving design. Hardware virtualization  supports. ARM BASED PRODUCTS . Sources : http://embeddedcraft.org / http :// whatis.techtarget.com/definition/ARM-processor

22.   MIPS It includes MIPS I, MIPS II, MIPS III, MIPS IV, MIPS V, MIPS32, and MIPS64.  Key concepts: five-stage execution pipeline regular instruction set, all instructions are 32-bit no status register or instruction side-effects no complex instructions. only the load and store instruction access memory. optional coprocessors for system management and floating-point flat address space of 2^32 bytes of main memory MIPS - M icroprocessor without I nterlocked P ipeline S tages Sources : http:// embeddedcraft.org/ https :// tams.informatik.unihamburg.de/applets/webdemos/mips.html

23. DISCUSSION

24. PERFORMANCE EQUATION Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/risccisc/index.html

25. RISC & CISC CONVERGENCE With time and developments, it was observed that the line of distinction between two hardware began to blur. In fact two hardware seem to have adopted the strategies of the other. CISC - now executes more than one instruction within a single clock. This also allows CISC chips to make use of pipelining . With other technological improvements, it is now possible to fit many more transistors on a single chip. RISC - incorporate more complicated , CISC-like commands.  RISC C ISC Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/developments/index.html

26. CONCLUSION Experts’ talk - we are in a "post-RISC " era , in which the two styles have become so similar that distinguishing between them is no longer relevant.  RISC chips still retain some important traits. - utilize uniform, single-cycle instructions. - register-to-register , load/store architecture. - still have a large number of general purpose registers. Sources : https://cs.stanford.edu/people/eroberts/courses/soco/projects/risc/developments/index.html