RISC Vs CISC Computer architecture and design

RISC Vs CISC Computer architecture and design

1. RISC Vs CISC

2. Classification of Microprocessors:   T he classification based on the word length, the architecture i.e. Instruction Set of the microprocessor. These are categorized into RISC and CISC. 

3. Before start ! RISC is the way to make hardware simpler whereas CISC is the single instruction that handles multiple work.

4. RISC Definition stands for R educed I nstruction S et C omputers. is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions, The main idea behind this, is to simplify hardware by using an instruction set composed of a few basic steps for loading, evaluating, and storing operations just like a load command will load data, a store command will store the data.  Examples:  SPARC, POWER PC, etc.

5. Characteristics of RISC Simpler instruction, hence simple instruction decoding. Instruction comes undersize of one word. Instruction takes a single clock cycle to get executed. More general-purpose registers. Simple Addressing Modes. Fewer Data types. A pipeline can be achieved. 

6. Advantages of RISC Simpler instructions:  RISC processors use a smaller set of simple instructions, which makes them easier to decode and execute quickly. This results in faster processing times. Faster execution:  Because RISC processors have a simpler instruction set, they can execute instructions faster than CISC processors. Lower power consumption:   RISC processors consume less power than CISC processors, making them ideal for portable devices.

7. Disadvantages of RISC More instructions required:  RISC processors require more instructions to perform complex tasks than CISC processors. Increased memory usage: RISC processors require more memory to store the additional instructions needed to perform complex tasks. Higher cost:   Developing and manufacturing RISC processors can be more expensive than CISC processors.

8. Complex Instruction Set Architecture (CISC) The main idea is that a single instruction will do all loading, evaluating, and storing operations just like a multiplication command will do stuff like loading data, evaluating, storing it, hence it’s complex.  Examples:  Intel architecture, AMD

9. Characteristics of CISC Complex instruction, hence complex instruction decoding. Instructions are larger than one-word size. Instruction may take more than a single clock cycle to get executed. Less number of general-purpose registers as operations get performed in memory itself. Complex Addressing Modes. More Data types. 

10. Advantages of CISC Reduced code size:   CISC processors use complex instructions that can perform multiple operations, reducing the amount of code needed to perform a task. More efficient memory:  Because CISC instructions are more complex, they require fewer instructions to perform complex tasks, This can result in more memory-efficient code. Widely used:   CISC processors have been in use for a longer time than RISC processors, so they have a larger user base and more available software.

11. Disadvantages of CISC Slower execution:  CISC processors take longer to execute instructions because they have more complex instructions and need more time to decode them. More complex design:  CISC processors have more complex instruction sets, which makes them more difficult to design and manufacture. Higher power consumption:  CISC processors consume more power than RISC processors because of their more complex instruction sets.

12. Example: Multiplying Two Numbers in Memory The figure in the next slide is a diagram representing the storage scheme for a generic computer. The main memory is divided into locations numbered from (row) 1: (column) 1 to (row) 6: (column) 4. The execution unit is responsible for carrying out all computations. However, the execution unit can only operate on data that has been loaded into one of the six registers (A, B, C, D, E, or F).

13. Example: Multiplying Two Numbers in Memory Let's say we want to find the product of two numbers one stored in location 2:3 and another stored in location 5:2 then store the product back in the location 2:3.

14. Cont. example: The CISC Approach The primary goal of CISC architecture is to complete a task in as few lines of assembly as possible. This is achieved by building processor hardware that is capable of understanding and executing a series of operations. For this particular task, a CISC processor would come prepared with a specific instruction (we'll call it "MULT"). When executed, this instruction loads the two values into separate registers, multiplies the operands in the execution unit, stores the product in the appropriate register. Thus, the entire task of multiplying two numbers can be completed with one instruction: MULT 2:3, 5:2

15. For instance, if we let "a" represent the value of 2:3 and "b" represent the value of 5:2, then this command is identical to the C statement "a = a * b." One of the primary advantages of this system is that the compiler has to do very little work to translate a high-level language statement into assembly. Because the length of the code is relatively short, very little RAM is required to store instructions. The emphasis is put on building complex instructions directly into the hardware. Cont. example: The CISC Approach

16. RISC processors only use simple instructions that can be executed within one clock cycle. Thus, the "MULT" command described above could be divided into three separate commands "LOAD," which moves data from the memory bank to a register, "PROD," which finds the product of two operands located within the registers, and "STORE,“ which moves data from a register to the memory banks. Cont. example: The RISC Approach

17. In order to perform the exact series of steps described in the CISC approach, a programmer would need to code four lines of assembly: LOAD A, 2:3 LOAD B, 5:2 PROD A, B STORE 2:3, A Cont. example: The RISC Approach

18. At first, this may seem like a much less efficient way of completing the operation. Because there are more lines of code, more RAM is needed to store the assembly level instructions. The compiler must also perform more work to convert a high-level language statement into code of this form. Cont. example: The RISC Approach

19. However, the RISC strategy also brings some very important advantages. 1 Because each instruction requires only one clock cycle to execute, the entire program will execute in approximately the same amount of time as the multi-cycle "MULT" command. These RISC "reduced instructions" require less transistors of hardware space than the complex instructions, leaving more room for general purpose registers. Because all of the instructions execute in a uniform amount of time (i.e. one clock), pipelining is possible. Cont. example: The RISC Approach

20. 2- Separating the "LOAD" and "STORE" instructions actually reduces the amount of work that the computer must perform. Cont. example: The RISC Approach

21. 3- After a CISC-style "MULT" command is executed, the processor automatically erases the registers. If one of the operands needs to be used for another computation, the processor must re-load the data from the memory bank into a register. In RISC, the operand will remain in the register until another value is loaded in its place. Cont. example: The RISC Approach

22. Difference between CISC and RISC Here, are important differences between CISC vs. RISC

23. Difference between CISC and RISC RISC CISC Focus on software Focus on hardware Uses only Hardwired control unit Uses hardwired &  microprogrammed control unit Fixed sized instructions Variable sized instructions An instruction fit in one word. (mostly 32-bits) Instructions are larger than the size of one word Requires more number of registers Requires less number of registers

24. Difference between CISC and RISC RISC CISC Simple addressing formats are supported. Only base and displacement addressing is allowed. Multiple formats are supported for specifying operands. A memory operand specifier can have many different combinations of displacement, base, and index register. Simple and limited addressing modes.  Complex and more addressing modes.

25. Difference between CISC and RISC RISC CISC It consumes low power. It consumes more/high power. RISC is highly pipelined. CISC is less pipelined. RISC required more  RAM for storing codes for storing codes . CISC required less RAM for storing codes. Code size is large Code size is small An instruction executed in a single clock cycle Instruction takes more than one clock cycle

26. CISC and RISC Convergence Because a number of advancements are used by both RISC  and  CISC processors, the lines between the two architectures have begun to blur. In fact, the two architectures almost seem to have adopted the strategies of the other. Because processor speeds have increased, CISC chips are now able to execute more than one instruction within a single clock. This also allows CISC chips to make use of pipelining.

27. CISC and RISC Convergence With other technological improvements, it is now possible to fit many more transistors on a single chip. This gives RISC processors enough space to incorporate more complicated, CISC-like commands. RISC chips also make use of more complicated hardware, making use of extra functional units for superscalar execution. All of these factors have led some groups to argue that we are now in a "post-RISC" era, in which the two styles have become so similar that distinguishing between them is no longer relevant.

28. CISC and RISC Convergence However, it should be noted that RISC chips still retain some important behaviors. RISC chips strictly utilize uniform, single-cycle instructions. They also retain the register-to-register, load/store architecture. despite their extended instruction sets, RISC chips still have a large number of general purpose registers.

29. RISC Roadblocks Despite the advantages of RISC based processing, RISC chips took over a decade to gain a foothold in the commercial world. This was largely due to a lack of software support. although Apple's Power Macintosh line featured RISC-based chips and Windows NT was RISC compatible, Windows 3.1 and Windows 95, and later versions were designed with CISC processors in mind. Many companies were unwilling to take a chance with the emerging RISC technology.

30. RISC Roadblocks Without commercial interest, processor developers were unable to manufacture RISC chips in large enough volumes to make their price competitive. Another major setback was the presence of Intel. Although their CISC chips were becoming increasingly awkward and difficult to develop, Intel had the resources to plow through development and produce powerful processors. Although RISC chips might surpass Intel's efforts in specific areas, the differences were not great enough to persuade buyers to change technologies.

31. EPIC It stands for Explicitly Parallel Instruction Computing The best features of RISC and CISC processors are combined in the architecture. It implements parallel processing of instructions rather than using fixed-length instructions. The working of EPIC processors is supported by using a set of complex instructions that contain both basic instructions as well as the information of execution of parallel instructions. It substantially increases the efficiency of these processors.