Semiconductor technology for electrcial engineering.pptx

Semiconductor technology
Electrical engineering notes

1. EE3151 BASICS OF ELECTRICAL AND ELECTRONICS ENGINEERING Unit 3: Analog and Digital Electronics

2. Semiconductors Semiconductors. A semiconductor material is one whose electrical properties lie in between those of insulators and good conductors. Examples are : germanium and silicon. In terms of energy bands, semiconductors can be defined as those materials which have Almost an empty conduction band and Almost filled valence band with a very narrow energy gap (of the order of 1 eV ) separating the two. At 0ºK, there are no electrons in the conduction band and the valence band is completely filled.

3. Semiconductors with increase in temperature, width of the forbidden energy bands is decreased so that some of the electrons are liberated into the conduction band. In other words, conductivity of semiconductors increases with temperature. Such departing electrons leave behind positive holes in the valence band .Hence, semiconductor current is the sum of electron and hole currents flowing in opposite directions.

4. Semiconductors Semiconductor: Special class of material having conductivity between that of a good conductor and insulator . Types: Single crystal: Ge.Si Compound semiconductors: 2 or more semiconductor material of different atomic structure. Ex: Gallium Arsenide( Ga As), Cadmium sulfide( cds ). Gallium Nitride( Ga N), Gallium Arsenide phosphide ( GaAs P). Commonly used: Ge,SI,GaAs

5. Classification of Semiconductors

6. Intrinsic Semiconductor An intrinsic semiconductor is one which is made of the semiconductor material in its extremely pure form. Common examples of such semiconductors are : pure germanium and silicon which have forbidden energy gaps of 0.72 eV and 1.1 eV respectively. The energy gap is so small that even at ordinary room temperature, there are many electrons which possess sufficient energy to jump across the small energy gap between the valence and the conduction bands. However, it is worth noting that for each electron liberated into the conduction band, a positively charged hole is created in the valence band .

7. E xtrinsic semiconductor A semiconductor material that has been subjected to the doping process is called an extrinsic material. Types: Ptype, N type

8. n -Type Material An n -type material is created by introducing impurity elements that have five valence electrons ( pentavalent ), such as antimony , arsenic , and phosphorus. Each is a member of a subset group of elements in the Periodic Table of Elements referred to as Group V because each has five valence electrons. There is, however, an additional fifth electron due to the impurity atom, which is unassociated with any particular covalent bond. This remaining electron, loosely bound to its parent (antimony) atom, is relatively free to move within the newly formed n -type material. Since the inserted impurity atom has donated a relatively “free” electron to the structure: it is called donar atom

9. n -Type Material Diffused impurities with five valence electrons are called donor atoms. It is important to realize that even though a large number of free carriers have been established in the n -type material, it is still electrically neutral since ideally the number of positively charged protons in the nuclei is still equal to the number of free and orbiting negatively charged electrons in the structure.

10. n -Type Material In an n-type material the electron is called the majority carrier and the hole the minority carrier.

11. p -Type Material The p -type material is formed by doping a pure germanium or silicon crystal with impurity atoms having three valence electrons. The elements most frequently used for this purpose are boron , gallium , and indium . Each is a member of a subset group of elements in the Periodic Table of Elements referred to as Group III because each has three valence electrons.

12. p -Type Material In a p-type material the hole is the majority carrier and the electron is the minority carrier.

13. p -Type Material T here is now an insufficient number of electrons to complete the covalent bonds of the newly formed lattice. The resulting vacancy is called a hole and is represented by a small circle or a plus sign, indicating the absence of a negative charge. Since the resulting vacancy will readily accept a free electron: The diffused impurities with three valence electrons are called acceptor atoms. The resulting p -type material is electrically neutral

14. Formation of the Depletion Region- PN Junction

15. The potential difference of the electric field across the depletion region is the amount of voltage required to move electrons through the electric field. This potential difference is called the barrier potential and is expressed in volts Amount of voltage equal to the barrier potential and with the proper polarity must be applied across a pn junction before electrons will begin to flow across the junction The barrier potential of a pn junction depends on several factors, including the type of semiconductive material, the amount of doping, and the temperature. The typical barrier potential is approximately 0.7 V for silicon and 0.3 V for germanium at 25 C;

16. Symbol – PN Junction Diode

17. Working & characteristics of PN junction diode This region of uncovered positive and negative ions is called the depletion region due to the depletion of carriers in this region. Since the diode is a two-terminal device, the application of a voltage across its terminals leaves three possibilities: no bias (V D 0 V), forward bias (V D > 0 V), and reverse bias (V D <0 V).

18. No BIAS

19. No-bias conditions for a semiconductor diode.

20. Reverse-Bias Condition ( V D < 0 V)

21. Reverse-Bias Condition ( V D < 0 V) The term saturation comes from the fact that it reaches its maximum level quickly and does not change significantly with increase in the reverse-bias potential,. Reverse-bias conditions for a semiconductor diode

22. The extremely small reverse current in a reverse-biased diode is due to the minority carriers from thermally generated electron-hole pairs.

23. Forward-biased p–n junction:

24. Forward-Bias Condition ( VD > 0 V) T he general characteristics of a semiconductor diode can be defined by the following equation, referred to as Shockley’s equation, for the forward- and reverse-bias regions: I s is the reverse saturation current V D is the applied forward-bias voltage across the diode ή is an ideality factor, which is a function of the operating conditions and physical construction; it has a range between 1 & 2 k is Boltzmann’s constant = 1.38 * 10 - 23 J/K T K = absolute temperature in kelvins = 273 + the temperature in °C q is the magnitude of electronic charge = 1.6 * 10 - 19 C

25. Temperature Effects For a forward-biased diode, as temperature is increased, the forward current increases for a given value of forward voltage. Also, for a given value of forward current, the forward voltage decreases. The blue curve is at room temperature(25 C) and the red curve is at an elevated temperature The barrier potential decreases by 2 mV for each degree increase in temperature. For a reverse-biased diode, as temperature is increased, the reverse current increases.

26. Temperature effect on the diode V-I characteristic.

27. Temperature effect on the diode V-I characteristic.

28. AVALANCHE BREAKDOWN Avalanche breakdown Avalanche breakdown occurs in moderately and lightly doped pn junctions with a wide depletion region. Electron hole pairs thermally generated in the depletion region are accelerated by the external reverse bias. These electron can interact with other Si atoms and if they have sufficient energy can knock off electrons from these Si atoms. These electrons imparts sufficient energy to disrupt a covalent bond.This process is called impact ionization and leads to production of a large number of electrons. This causes the rapid rise in current.

29. ZENER BREAKDOWN- second mechanism that disrupts the covalent bonds. With increase in doping concentration the breakdown mechanism, changes from Avalanche to a tunneling mechanism. This is called a Zener breakdown. This is because the depletion width decreases with dopant concentration..Electrons tunnel from the valence band on the p side to the conduction band on the n side, driven by the externally applied reverse bias. Tunneling also leads to a large increase in current. The use of a sufficiently strong electric field at the junction can cause a direct rupture of the bond. If the electric field exerts a strong force on a bound electron, the electron can be torn from the covalent bond thus causing the number of electron-hole pair combinations to multiply. This mechanism is called high field emission or Zener breakdown. The value of reverse voltage at which this occurs is controlled by the amount of doping of the diode. A heavily doped diode has a low Zener breakdown voltage, while a lightly doped diode has a high Zener breakdown voltage.

30. Vz - Nominal Zener voltage Specific for I ZT ; I ZT = Zener test current ; related to VZ; ∆V Z = Change in Zener voltage; I Z = current going through the diode for different values of V Z ; Z Z = Zener impedance Δ V Z / Δ I Z I ZK = Minimum dc current; I ZM = Maximum DC current P D (max) –max power dissipated =V Z * I ZM

31. The  Zener Diode  is used in its “reverse bias” or reverse breakdown mode, i.e. the diodes anode connects to the negative supply. From the I-V characteristics curve above, we can see that the zener diode has a region in its reverse bias characteristics of almost a constant negative voltage regardless of the value of the current flowing through the diode. This voltage remains almost constant even with large changes in current providing the zener diodes current remains between the breakdown current I Z(min)  and its maximum current rating I Z(max) . The fact that the voltage across the diode in the breakdown region is almost constant turns out to be an important characteristic of the zener diode as it can be used in the simplest types of voltage regulator applications. The function of a voltage regulator is to provide a constant output voltage to a load connected in parallel with it in spite of the ripples in the supply voltage or variations in the load current.

32. A Zener diode will continue to regulate its voltage until the diodes holding current falls below the minimum I Z(min)  value in the reverse breakdown region. Zener Diode Regulator Zener Diodes  can be used to produce a stabilised voltage output with low ripple under varying load current conditions. By passing a small current through the diode from a voltage source, via a suitable current limiting resistor (R S ), the Zener diode will conduct sufficient current to maintain a voltage drop of  V out

33. Zener as Voltage Regulator Lab component available so included here; Not required for theory

34. Analysis of Circuit- Zener diodes Step 1:The state of the diode must be determined. OC Zener diode and find the voltage across it If V > VZ , the Zener diode is “on” and the equivalent model of Fig. 1 can be substituted. If V < VZ , the diode is “off” and the open-circuit equivalence is substituted. Step 2: Substitute the appropriate equivalent circuit and solve for the desired unknowns

35. Zener diode as shunt regulator Fixed Vi , Variable RL Due to the offset voltage V Z , there is a specific range of resistor values (and therefore load current) which will ensure that the Zener is in the “on” state. Too small a load resistance R L will result in a voltage VL across the load resistor less than V Z , and the Zener device will be in the “off” state. To determine the minimum load resistance that will turn the Zener diode on, simply calculate the value of R L that will result in a load voltage V L = V Z .

36. Solving for RL , we have Any load resistance value greater than the R L obtained from above Eq. will ensure that the Zener diode is in the “on” state and the diode can be replaced by its V Z source equivalent. The condition defined by above Eq. establishes the minimum R L but in turn specifies the maximum I L

37. Once the diode is in the “on” state, the voltage across R remains fixed at The Zener current I Z is minimum when I L is a maximum and a maximum I Z when I L is a minimum value since I R is constant. Since I Z is limited to I ZM as provided on the data sheet, it does affect the range of R L and therefore I L . Substituting I ZM for I Z establishes the minimum I L as

38. Fixed R L , Variable V i For fixed values of R L in Fig the voltage V i must be sufficiently large to turn the Zener diode on. The minimum turn-on voltage V i = V i min is determined by The maximum value of V i is limited by the maximum Zener current I ZM . Since I ZM = I R - I L , Since I L is fixed at V Z /R L and I ZM is the maximum value of I Z , the maximum V i is defined by

39. (a) For the Zener diode network of Fig shown below. determine V L , V R , I Z , and P Z . (b) Repeat part (a) with RL = 3 k.

40. Since V = 8.73 V is less than VZ = 10 V, the diode is in the “off” state as shown on the characteristics . open-circuit the Zener diode

41. Since V 12 V is greater than VZ 10 V, the diode is in the “on” state and the network of Fig. will result. The power dissipated, which is less than the specified P ZM = 30 mW .

42. For the network , determine the range of R L and I L that will result in V RL being maintained at 10 V. Determine the maximum wattage rating of the diode. To determine the value of R L that will turn the Zener diode on,

43. Determine the range of values of V i that will maintain the Zener diode in the “on” state.

44. BJT

45. BJT The transistor was developed by Dr.Shockley along with Bell Laboratories team in 1951 Term BJT- Bipolar Junction Transistor: BIpolar -refers to the condition that the current conduction is due to both electrons and holes. Junction- has 2 PN junction Transistor= Transfer+resistor ; In active mode, (amplifier)Device transfer current from low input impedance circuit to high impedance circuit. Resulting in amplification The transistor is a main building block of all modern electronic systems

46. Construction-BJT There are two basic types of transistors : the bipolar junction transistor (BJT) the field-effect transistor (FET) The bipolar junction transistor is used in two broad areas of electronics : (1) as a linear amplifier to boost an electrical signal and (2) as an electronic switch.

47. Structure of PNP NPN transistor

48. The emitter base depletion layer penetrates slightly into the emitter as it is a heavily doped region where as it penetrates deeply into the base as it is a lightly doped region Similarly the collector- base depletion layer penetrates more into the base region and less into the collector region The emitter- base depletion layer width is smaller than the that of collector base depletion layer

49. Symbol –NPN, PNP transistor

50. Three types of circuit connections

51. Mode EB J BC J Cutoff Reverse Reverse Active Forward Reverse Saturation Forward Forward Modes of operation

52. Working –NPN transistor (CB configuration)

53. CB configuration

54. CE Configuration

55. Relation between α and β

56. CC Configuration

57. BJT will satisfy KCL and KVL equation across its terminals.

58. Leakage Currents in a Transistor

59. Leakage Currents in a Transistor Consider CE Configuration, It is found that despite I B = 0, there is a leakage current from collector to emitter. It is called I CEO , the subscripts CEO standing for ‘Collector to Emitter with base Open’.

60. Thermal Runaway For a CE circuit I C = β I B + (1 + β) I CO The leakage current is extremely temperature-dependent. It almost doubles for every 6°C rise in temperature in Ge and for every 10°C rise in Si . Any increase in I CO is magnified (1 + β) times i.e . 300 to 500 times. Even a slight increase in I CO will affect IC considerably. As I C increases, collector power dissipation increases which raises the operating temperature that leads to further increase in I C . If this succession of increases is allowed to continue, soon I C will increase beyond safe operating value thereby damaging the transistor itself—a condition known as thermal runaway .

61. Transistor Static Characteristics There are the curves which represents relationship between different d.c. currents and voltages of a transistor. These are helpful in studying the operation of a transistor when connected in a circuit. The important characteristics of a transistor are : 1. Input characteristic, 2. Output characteristics 3. Current Transfer Characteristic

62. Common Base Test Circuit

63. Input characteristics:

64. Output characteristics :

65. Current Transfer Characteristic

66. Common Emitter Test Circuit

67. Input characteristics:

68. Output characteristics –CE The value of output resistance Rout (= Δ V CE / Δ I C ) over the near horizontal part of the characteristic varies from 10 k Ω to 50 k Ω

69. Current Transfer Characteristic:

70. CC test circuit

71. Input characteristics For CC configuration, VCB is dependant on VCE; VCB=VCE-VBE; For constant IB , fixed VBE as VCE increases, VCB increases in input charact ; As VCB increases, IB is decreased. (Discuss Early effect)

72. Output characteristics – Similar to CE Configuration

73. JFET

74. TYPES OF FETS Junction field-effect transistor (JFET) n channel p channel Metal-oxide-semiconductor field-effect transistor (MOSFET). D-MOSFET: Depletion MOSFET n channel p channel E-MOSFET: Enhancement MOSFET n channel p channel

75. Similarities: Amplifiers Switching devices Impedance matching circuits Differences : FETs are voltage controlled devices. BJTs are current controlled devices. FETs have a higher input impedance. BJTs have higher gains. FETs are less sensitive to temperature variations and are more easily integrated on ICs. FETs are generally more static sensitive than BJTs. FETs vs . BJTs

76. Basic Structure / Construction of JFET Three terminal semiconductor device in which current conduction is by one type of carrier i.e electrons or holes; The three terminals are drain, source, gate JFET consists of p type or n type semiconductor bar with two pn junctions on the side; The semiconductor bar forms the conducting channel for charge carriers; If Si bar is of n type, it is called n channel JFET; If Si bar is of p type, it is called p channel JFET;

77. In case of n channel , two p regions are diffused and both the p regions are connected to form gate lead; In case of p channel , two n regions are diffused and both the n regions are connected to form gate lead; Ohmic contacts (direct electrical connection) are made at the ends of the Si bar; one is source and the other is drain. When Potential difference is established, current flows through the channel; The current conduction is due to majority carriers; holes in p channel JFET and electrons in n channel JFET; Source : Terminal through which majority carriers enter the Si bar Drain: Terminal through which majority carrier leave Channel: It is the space between the two gate regions through which the majority carriers flow from the source to the drain terminal. Gate: These are two internally connected heavily doped impurity region which form 2 pn junctions; Gate is always Reverse biased;

78. Structure , symbol of JFET

79. Structure , symbol of JFET

80. Working/ characteristics of n Channel JFET Gate terminal is always reverse biased; Source is connected to – ve of the drain voltage for obtaining the electrons; Case 1: V GS = 0 V; V DS =0 In this case I D =0 because V DS =0 Depletion region around PN junction have equal thickness and symmetrical . Case 2 : V GS = 0 V; V DS is increased from zero Gate and source terminals are directly connected together to establish V GS = 0 V;

81. When V DD =V DS is applied , electrons which are majority carriers flow from source to drain whereas conventional drain current flows through the channel from D to S; Path of the current clearly shows that I D = I S Flow of charge through channel is limited by the resistance of the n channel between source and drain; It is important to note that the depletion region is wider near the top of both p type regions; The reason for the change in width of the region is best described through the help of Fig. Assuming a uniform resistance in the n- channel, the resistance of the channel can be broken down to the divisions appearing in Fig.

82. current ID will establish the voltage levels through the channel as indicated on the same figure. The result is that the upper region of the p- type material will be reverse biased by about 1.5 V, with the lower region only reverse-biased by 0.5 V. Recall from the discussion of the diode operation that the greater the applied reverse bias, the wider the depletion region—hence the distribution of the depletion region as shown in Fig. The fact that the p-n junction is reverse-biased for the length of the channel results in a gate current of zero amperes as shown in the same figure. The fact that I G = 0 A is an important characteristic of the JFET.

83. As the voltage V DS is increased from 0 to a few volts, the current will increase as determined by Ohm’s law. Since the resistance of the channel remains constant. As V DS increases and approaches a level referred to as V P in Fig, the depletion regions will widen, causing a noticeable reduction in the channel width. The reduced path of conduction causes the resistance to increase . The more horizontal the curve, the higher the resistance, suggesting that the resistance is approaching “infinite” ohms in the horizontal region.

84. If V DS is increased to a level where it appears that the two depletion regions would “touch” as shown in Fig , a condition referred to as pinch-off will result. The level of V DS that establishes this condition is referred to as the pinch-off voltage and is denoted by V P In actuality, the term pinch-off is a misnomer in that it suggests the current I D is pinched off and drops to 0 A. As shown in Fig. this is hardly the case— I D maintains a saturation level defined as I DSS . In reality a very small channel still exists, with a current of very high density. The fact that I D does not drop off at pinch-off and maintains the saturation level indicated in Fig. Is verified by the following fact: The absence of a drain current would remove the possibility of different potential levels through the n -channel material to establish the varying levels of reverse bias along the p-n junction. The result would be a loss of the depletion region distribution that caused pinch-off in the first place.

85. As V DS is increased beyond V P , the region of close encounter between the two depletion regions will increase in length along the channel, but the level of I D remains essentially the same. In essence, therefore, once V DS = V P the JFET has the characteristics of a current source. The current is fixed at I D = I DSS , But the voltage V DS (for levels VP ) is determined by the applied load. The choice of notation I DSS is derived from the fact that it is the D rain-to- S ource current with a S hort-circuit connection from gate to source. I DSS is the maximum drain current for a JFET and is defined by the conditions V GS = 0 V and V DS = |VP|.

86. Case 3: V GS <0 V; V DS =+ ve ; The voltage from gate to source, denoted V GS , is the controlling voltage of the JFET. For the n- channel device the controlling voltage V GS is made more and more negative from its V GS =0 V level. In other words, the gate terminal will be set at lower and lower potential levels as compared to the source. A negative voltage of -1 V has been applied between the gate and source terminals for a low level of V DS . The effect of the applied negative-bias V GS is to establish depletion regions similar to those obtained with V GS = 0V but at lower levels of V DS .

87. Therefore, the result of applying a negative bias to the gate is to reach the saturation level at a lower level of V DS The resulting saturation level for I D has been reduced and in fact will continue to decrease as V GS is made more and more negative. Note how the pinch off voltage continues to drop in a parabolic manner as V GS becomes more and more negative. when V GS =-V P will be sufficiently negative to establish a saturation level that is essentially 0 mA, and for all practical purposes the device has been “turned off.”

88. The level of V GS that results in I D = 0 mA is defined by V GS = V P , with V P being a negative voltage for n-channel devices and a positive voltage for p-channel JFETs. On most specification sheets the pinch-off voltage is specified as V GS (off) rather than V P . The region to the right of the pinch-off locus is the region typically employed in linear amplifiers (amplifiers with minimum distortion of the applied signal) and is commonly referred to as the constant-current, saturation, or linear amplification region.

89. Voltage-Controlled Resistor The region to the left of the pinch-off locus is referred to as the ohmic or voltage-controlled resistance region. In this region the JFET can actually be employed as a variable resistor (possibly for an automatic gain control system) whose resistance is controlled by the applied gate-to-source voltage. The slope of each curve and therefore the resistance of the device between drain and source for V DS < V P is a function of the applied voltage V GS . As V GS becomes more and more negative, the slope of each curve becomes more and more horizontal, corresponding with an increasing resistance level. The following equation will provide a good first approximation to the resistance level in terms of the applied voltage V GS . ro = is the resistance with VGS =0 V and rd = the resistance at a particular level of VGS .

90. Transfer characteristics - JFET The transfer curve can be obtained using Shockley’s equation or from the output characteristics

91. MOSFET

92. There are two types of FETs: JFETs and MOSFETs. MOSFETs are further broken down into depletion type and enhancement type based on basic mode of operation. MOSFET stands for m etal- o xide- s emiconductor- f ield- e ffect t ransistor. The main drawback of JFET is that gate can only be reverse biased for proper operation of the device. It can only have negative operation for n channel and positive gate operation for p channel; i.e we can only decrease the width of the channel and decrease the conductivity of the channel from its zero bias size;

93. But there is a type of FET that can be operated to enhance the width of the channel and hence increase the conductivity of the channel. ----- MOSFET. Depletion-type MOSFET, which happens to have characteristics similar to those of a JFET between cutoff and saturation at IDSS but then has the added feature of characteristics that extend into the region of opposite polarity for V GS .

94. Basic Construction - n- channel depletion-type MOSFET A slab of p- type material is formed from a silicon base and is referred to as the substrate. It is the foundation upon which the device will be constructed. In some cases the substrate is internally connected to the source terminal. However, many discrete devices provide an additional terminal labeled SS , resulting in a four-terminal device. The source and drain terminals are connected through metallic contacts to n- doped regions linked by an n- channel.

95. The gate is also connected to a metal contact surface but remains insulated from the n- channel by a very thin silicon dioxide (SiO2) layer. SiO2 is a particular type of insulator referred to as a dielectric that sets up opposing (as revealed by the prefix di-) electric fields within the dielectric when exposed to an externally applied field. The fact that the SiO2 layer is an insulating layer reveals the following fact: There is no direct electrical connection between the gate terminal and the channel of a MOSFET. It is the insulating layer of SiO2 in the MOSFET construction that accounts for the very desirable high input impedance of the device.

96. The very high input impedance continues to fully support the fact that the gate current (IG) is essentially zero amperes for dc-biased configurations. The reason for the label metal-oxide-semiconductor FET is now fairly obvious: metal for the drain, source, and gate connections to the proper surface—in particular, the gate terminal and the control to be offered by the surface area of the contact, the oxide for the silicon dioxide insulating layer, and the semiconductor for the basic structure on which the n- and p-type regions are diffused. The insulating layer between the gate and channel has resulted in another name for the device: insulated gate FET or IGFET.

97. Graphic Symbol of depletion type MOSFET

98. Basic Operation and Characteristics The gate-to-source voltage is set to zero volts by the direct connection from one terminal to the other, and a voltage VDS is applied across the drain-to-source terminals. The result is an attraction for the positive potential at the drain by the free electrons of the n- channel and a current similar to that established through the channel of the JFET. In fact, the resulting current with VGS 0 V continues to be labeled as I DSS

99. V GS has been set at a negative voltage such as 1 V. The negative potential at the gate will tend to pressure electrons toward the p- type substrate (like charges repel) and attract holes from the p- type substrate (opposite charges attract) as shown in Fig. Depending on the magnitude of the negative bias established by V GS , a level of recombination between electrons and holes will occur that will reduce the number of free electrons in the n- channel available for conduction.

100. The more negative the bias, the higher the rate of recombination. The resulting level of drain current is therefore reduced with increasing negative bias for V GS for V GS =- 1 V, -2 V, and so on, to the pinch-off level of -6 V. The resulting levels of drain current and the plotting of the transfer curve proceeds exactly as described for the JFET. For positive values of V GS , the positive gate will draw additional electrons (free carriers) from the p- type substrate due to the reverse leakage current and establish new carriers through the collisions resulting between accelerating particles.

101. As the gate-to-source voltage continues to increase in the positive direction, the drain current will increase at a rapid rate. vertical spacing between the V GS = 0 V and V GS = 1 V curves is a clear indication of how much the current has increased for the 1-V change in V GS . Due to the rapid rise, the user must be aware of the maximum drain current rating since it could be exceeded with a positive gate voltage. That is, for the device considered the application of a voltage V GS =+ 4 V would result in a drain current of 22.2 mA, which could possibly exceed the maximum rating (current or power) for the device. As revealed above, the application of a positive gate-to-source voltage has “enhanced” the level of free carriers in the channel compared to that encountered with V GS = 0 V. For this reason the region of positive gate voltages on the drain or transfer characteristics is often referred to as the enhancement region, with the region between cutoff and the saturation level of I DSS referred to as the depletion region.

102. It is particularly interesting and helpful that Shockley’s equation will continue to be applicable for the depletion-type MOSFET characteristics in both the depletion and enhancement regions. For both regions, it is simply necessary that the proper sign be included with V GS in the equation. The transfer curve can be obtained using Shockley’s equation or from the output characteristics

103. p- Channel Depletion-Type MOSFET The construction of a p- channel depletion-type MOSFET is exactly the reverse of that n channel. There is an n- type substrate and a p- type channel. The source and drain terminals are connected through metallic contacts to p- doped regions linked by an p- channel. The gate is also connected to a metal contact surface but remains insulated from the p - channel by a very thin silicon dioxide (SiO2) layer.

104. The drain current will increase from cutoff at V GS = V P in the positive V GS region to I DSS and then continue to increase for increasingly negative values of V GS . Shockley’s equation is still applicable and requires simply placing the correct sign for both V GS and V P in the equation.

105. ENHANCEMENT-TYPE MOSFET Although there are some similarities in construction and mode of operation between depletion-type and enhancement-type MOSFETs, the characteristics of the enhancement- type MOSFET are quite different from anything obtained thus far. The transfer curve is not defined by Shockley’s equation, and the drain current is now cut off until the gate-to-source voltage reaches a specific magnitude. In particular, current control in an n- channel device is now effected by a positive gate-to-source voltage rather than the range of negative voltages encountered for n- channel JFETs and n- channel depletion-type MOSFETs

106. Basic Construction A slab of p-type material is formed from a silicon base and is again referred to as the substrate. As with the depletion-type MOSFET, the substrate is sometimes internally connected to the source terminal, while in other cases a fourth lead is made available for external control of its potential level. The source and drain terminals are again connected through metallic contacts to n-doped regions.

107. There is no channel between the two n-doped regions. This is the primary difference between the construction of depletion-type and enhancement-type MOSFETs— The SiO2 layer is still present to isolate the gate metallic platform from the region between the drain and source, but now it is simply separated from a section of the p- type material.

108. Basic Operation and Characteristics If V GS is set at 0 V and a voltage applied between the drain and source of the device ,the absence of an n- channel will result in a current of effectively zero amperes. It is not sufficient to have a large accumulation of carriers (electrons) at the drain and source (due to the n- doped regions) Since a path fails to exist between the two. With V DS some positive voltage, V GS at 0 V, and terminal SS directly connected to the source, there are in fact two reverse-biased p-n junctions between the n- doped regions and the p- substrate to oppose any significant flow between drain and source.

109. Both V DS and V GS have been set at some positive voltage greater than 0 V, establishing the drain and gate at a positive potential with respect to the source. The positive potential at the gate will pressure the holes (since like charges repel) in the p- substrate along the edge of the SiO2 layer to leave the area and enter deeper regions of the p- substrate. The result is a depletion region near the SiO2 insulating layer void of holes. However, the electrons in the p- substrate (the minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO2 layer.

110. The SiO2 layer and its insulating qualities will prevent the negative carriers from being absorbed at the gate terminal. As V GS increases in magnitude, the concentration of electrons near the SiO2 surface increases until eventually the induced n- type region can support a measurable flow between drain and source. The level of VGS that results in the significant increase in drain current is called the threshold voltage and is given the symbol V T . On specification sheets it is referred to as V GS (Th) Since the channel is nonexistent with V GS = 0 V and “enhanced” by the application of a positive gate-to-source voltage, this type of MOSFET is called an enhancement-type MOSFET. Both depletion- and enhancement-type MOSFETs have enhancement-type regions, but the label was applied to the latter since it is its only mode of operation.

111. As V GS is increased beyond the threshold level, the density of free carriers in the induced channel will increase, resulting in an increased level of drain current. If we hold V GS constant and increase the level of V DS , the drain current will eventually reach a saturation level as occurred for the JFET and depletion-type MOSFET. The leveling off of I D (Saturation of drain current) is due to a pinching-off process depicted by the narrower channel at the drain end of the induced channel.

112. Applying Kirchhoff’s voltage law to the terminal voltages of the MOSFET, we find that If V GS is held fixed at some value such as 8 V and V DS is increased from 2 to 5V, the voltage V DG [refer above Eq. ] will drop from 6 to 3 V and the gate will become less and less positive with respect to the drain. This reduction in gate-to-drain voltage will in turn reduce the attractive forces for free carriers (electrons) in this region of the induced channel, causing a reduction in the effective channel width. Eventually, the channel will be reduced to the point of pinch-off and a saturation condition will be established as described earlier for the JFET and depletion-type MOSFET.

113. Any further increase in V DS at the fixed value of V GS will not affect the saturation level of I D until breakdown conditions are encountered. The saturation level for V DS is related to the level of applied V GS by the eqn given below: For a fixed value of V T , then the higher the level of V GS , the more the saturation level for V DS , as shown in Fig. by the locus of saturation levels.

114. For values of V GS less than the threshold level, the drain current of an enhancement- type MOSFET is 0 mA. As the level of V GS increased from V T to 8 V, the resulting saturation level for I D also increased from a level of 0 to 10 mA. For levels of V GS > VT, the drain current is related to the applied gate-to-source voltage by the following nonlinear relationship: Again, it is the squared term that results in the nonlinear (curved) relationship between I D and V GS . The k term is a constant that is a function of the construction of the device. The value of k can be determined from the following equation where ID (on) and VGS (on) are the values for each at a particular point on the characteristics of the device.

115. Consider the characteristics in above slide A general equation for I D for the characteristics and hence transfer characteristics for the considered device can be obtained using below equation

116. O PERATIONAL A MPLIFIERS

117. B ASIC C ONCEPTS Amplifi er : E l ectr o nic c i rcu i t th a t produ c es an outp u t quantity (voltage/current) in linear proportion to the input quantity. Op-amp: Operational amplifier , a high-gain amplifier with an output that corresponds to the difference between two input signals . V out = A(V + - V - ), A ~ 10 5 Integrated Circuit (IC): Collection of semiconductor electronic devices (diodes, transistors) combined with other circuit elements (R, L, C) printed in a single chip. A 136

118. R EAL L IFE A PPLICATIONS Microphone Amplifier Digital to Analog Converter 137

119. R EAL L IFE A PPLICATIONS Sensors e.g. Electronic Thermometer 138

120. R EAL L IFE A PPLICATIONS Automatic Light Operated Switch DC Volt Polarity Meter 139

121. R EAL L IFE A PPLICATIONS Control of Motors 140

122. R EAL L IFE A PPLICATIONS Music Players 141

123. R EAL L IFE A PPLICATIONS Analog Computer 142

124. R EAL L IFE A PPLICATIONS Current and Voltage Regulator 143

125. R EAL L IFE A PPLICATIONS Waveform Generator 11

126. O P -A MP I NTRODUCTION Multi-stage high-gain amplifier having a differential input and a single-ended output that draws power from an external supply voltage. Contains a number of transistor-based differential amplifier stages to achieve a very high voltage gain (~10 5 ). Contains several transistors, resistors, a few capacitors and diodes in it’s internal circuitry 145

127. O P -A MP I NTRODUCTION Differential Amplifier: Basic unit of the op-amp is a differential amplifier. A number of differential amplifiers are connected in cascade to form op-amp. V out = G v (V 1 – V 2 ) 146

128. O P -A MP I NTRODUCTION Op-amp Basic Circuit 147

129. O P -A MP I NTERNAL C IRCUIT The op-amp internal circuit can be divided into 3 stages: Input Stage The function of the input stage is to amplify the input difference, V p − V n , and convert it to a single-ended signal. Second Stage It further amplifies the signal and provides frequency compensation via the capacitor, C C Output Stage The output stage provides output current drive capability. 148

130. A differential amplifier is the input stage for the op-amp; it has two inputs and provides amplification of the difference voltage between the two inputs. The voltage amplifier is usually a class A amplifier that provides additional op-amp gain. Some op-amps may have more than one voltage amplifier stage. A push-pull class B amplifier is used for the output stage.

131. O P -A MP C HARACTERISTICS Common Mode Rejection Ratio (CMRR) CMRR-Important parameter of differential amplifier. Ability of differential amplifier to reject Common mode signals. The ratio of the differential gain to the common mode gain yields the common mode rejection ratio. Ideally CMRR should be infinite . 150 CMRR = A d / A c CMRR (dB) = 20 log 10 (A d / A c ) It is a measure of how well the op-amp suppresses identical signals on the inputs relative to differential input signals.

132. O P -A MP C HARACTERISTICS Differential mode operation: V o = A d V i A d typically very large Common mode operation: V o = A c V i A c << A d V o V i1 V i2 V d V o V i 151 Noise (any unwanted input signal) is common to both inputs, and hence is attenuated via the differential connection. For a good differential amplifier Ac=0;

133. O P -A MP C HARACTERISTICS 19 Output voltage V o = A d V d + A c V c V d = (V i1 – V i2 ) , V c = (V i1 + V i2 )/2 A d >> A c Common mode rejection The common signal is rejected while the difference of the signals is amplified. Noise (any unwanted input signal) is common to both inputs, and hence is attenuated via the differential connection. This feature is known as common mode rejection ratio (CMRR). V o V i1 V i2 V d

134. O P -A MP C HARACTERISTICS Slew Rate : The slew rate is the rate at which an operational amplifier can change an output when there is a change on the input. The µA741 device has a 0.5-V/ μs slew rate; Maximum rate of change of output voltage vs time . 153

135. O P -A MP C HARACTERISTICS In data sheet large signal slew rate is an indication of amplifier slew rate; Slew rate is different specification than small signal Bandwidth which considers the differential input signals of the range +/100mV or less.

136. O P -A MP C HARACTERISTICS There is a capacitor at the o/p stage of the OP-Amp; Capacitor takes time to charge and discharge; Hence o/p capacitor prevents o/p voltage to respond immediately to a fast changing i/p; slew rate is noticed when a large signal high frequency signal is applied. SR has impact on open loop and Closed loop applications; If RHS of the equation is less than SR, the o/p is always undistorted; If either the input signal , frequency of the signal is increased to exceed the SR, then o/p will be distorted; For o/p free of distortion, Slew rate determines the maximum frequency of operation for a desired o/p voltage swing

137. O P -A MP C HARACTERISTICS Input Bias Current: The average magnitude of the two base currents at the input terminals with the output at a specified level. 2 IB I I   I    IB IB Input bias current is a problem as it flows into external impedances and produces d.c. offset voltages , which add to system errors. Typically, I IB ~ 50 nA – 10 μA for low - high speed op amps. 156

138. O P -A MP C HARACTERISTICS Input Offset Current: The difference between the base currents into the two input terminals with the output at a specified level. It is because of an imbalance between the two input terminals e.g. due to slight differences in transistor characteristics or biasing elements. I IO = I IB + − I IB − e.g. For an input offset current I IO = 5 nA and input bias current I IB = 30 nA, the base currents at the two input terminals will be I B I B  I 2 2 I B I B I  I   30  5 / 2  32.5 nA  I I IO  I IO  30  5 / 2  27.5 nA 157

139. O P -A MP C HARACTERISTICS When the input is Zero, o/p is =0; But practically there exists some o/p voltage – O/P offset voltage ; Causes of O/P offset voltage: Spurious i/p noise signal which gets amplified by gain and available at O/P Mismatch between the two i/p terminals; Two collector currents of the transistor in i/p stage different causing differential voltage which is amplified further by other stages of OPAMP and available at o/p as offset voltage. It is a DC quantity; can be +/-ve; OFFSET VOLTAGE

140. Output offset voltage This error voltage gets amplified as if it is actual input ;

141. O P -A MP C HARACTERISTICS Input Offset Voltage: DC voltage that must be applied between the input terminals to provide a DC output voltage of zero . A direct consequence of a finite input offset current. If both inputs are grounded, the output voltage is not zero, but there is a small offset. V IO is normally depicted as a voltage source driving the non-inverting (+) input. 160

142. O P -A MP I NPUT -O UTPUT C HARACTERISTICS Ideal because offset is assumed as zero V CC V o -V EE Negative Saturation Positive Saturation V d Linear region 161 (slope = voltage gain) V in,max V in,min OPAMP amplifies the difference between the i/p signals

143. I DEAL O P -A MP V o V D AV D V P i N =0 V N i P =0 Infinite open-loop gain (A= ∞), Zero output impedance (Z out = 0), Can drive Infinite no of o/p devices. 162 Infinite input impedance (Z in = ∞) No loading effect Zero common-mode gain (CMRR = ∞) O/p common mode noise voltage is zero Infinite slew rate: O/p voltage change occurs simultaneously with i /p voltage change Infinite bandwidth :Can amplify signals from 0 to Inf Hz without attenuation. Zero input offsets ( V IO = 0, I IO = 0) & drift ( V drift = 0)

144. P RACTICAL O P -A MP 38 A is large but finite (~20,000 - 200,000), R in is large but finite (~0.3 - 2 MΩ) R out is small but non-zero (~75 Ω), Bandwidth is finite (Capacitances take effect) CMRR ~70-90 dB (~3000 - 30,000), Slew Rate <~0.5 V/μs V IO ~2-5 mV, I IO ~20-200 nA, I IB ~80-500 nA V o V D AV D out in x R r o out R r d in

145. C OMMONLY U SED IC S & P IN C ONFIGURATIONS 741: General purpose op-amp IC Used in general purpose amplifiers, active filters, arithmetic circuits, voltage comparators, waveform generators, regulated power supplies etc. 164

146. V IRTUAL G ROUND C ONCEPT V o ≤ |V CC | ~ 5 - 15 V e.g. for V o = 10 V & A = 10 5 , V D = 0.1 mV V o V D r d r o AV D I in +V CC 165 -V CC V D ~ 0 is a very good approximation in most cases (“virtual ground”). Thus, at the op-amp input terminals , there exists a virtual short circuit. Also, there is no current through the input terminals to a very good approximation i.e. I in ~ 0 .

147. Inverting Ampliier - V IRTUAL G ROUND C ONCEPT By the concept of virtual ground, i = 0 => i 1 = − i f and, v = v’ = v o R f R 1 v i v V ’ i f i 1 i 166 Gain=-Rf/R1,

148. Non inverting amplifier-GAIN – VIRTUAL GROUND CONCEPT v o R f R 1 v v’ v i 167 i f i 1 By the virtual ground concept, v = v’ = v i and i 1 = -i f  -v i / R 1 = ( v i – v o ) / R f  A v = v o /v i = 1 + (R f / R 1 )

149. N UMERICAL E XAMPLE 1 Problem: Given v i = 1 V in the circuit below. Find the output voltage v o and output current i o o R 1 v i v R 2 R 3 i o v i = = i v i   v o  v i 5 k 40 k  v o  9 V o o 2 k 4 k i  v  v o  v i i o  0.65 mA Soln: v = v’= v i = 1 V As i=0 , 40 kΩ 5 kΩ v 20 kΩ  168

150. CLOSED LOOP GAIN USING VIRTUAL GROUND CONCEPT v o R f R 1 v i v v ' i f i 1 By the virtual ground concept, v = v’ = and i 1 = -i f  v i / R 1 = -v o / R f 169  A CL = v o /v i = -(R f / R 1 ) IDEAL CASE:

151. N UMERICAL E XAMPLE Problem: Find v o for the circuit shown below Soln: Consider the inverting amplifier at the first op-amp 3 2 2 v 3 v R   R  v   v 170

152. N UMERICAL E XAMPLE Now for the second op-amp, the circuit reduces to As v = v’ = 0 , KCL at (−): => R 1 R 2  v 3   1 2 1 2 1 v R R v  v     2 2 1 1 o R R  v  v  v v o R 2 R 1 R 1 v 1 v 3 v v -v 2 v  -v  v  171 1 2   o R 1

153. Solved P r oblems 172

154. N UMERICAL 3 Problem: Determine v o in the op-amp circuit below. 173

155. => => Since, v a = v b = 2 V => Soln: KCL at node a: v a  v o  6  v a 40 k 20 k v a  v o  12  2 v a 174 v o  3 v a  12 v o  6  12   6 V

156. N UMERICAL 5 Problem : Determine the input impedance and output voltage for the op-amp circuit shown below. R L is the load resistance. 175

157. N UMERICAL 5 Soln: Since V − = 0, the input impedance is Z in = V in / I in = 5 kΩ V o  AV i 5 k A    R f    20 k   4  R   1  V o  100 m    4    400 mV I in V in 176 V −

158. OPEN LOOP APPLICATIONS- OP-AMP The value of A OL is extremely large often 200,000 or large ; Vo can’t exceed the positive or negative V CC ; For +/-15V supply, op-amp saturation voltage is +/-13V; Thus in open loop if Op-amp has to be operated as amplifier the V id ,max should be limited to +/-65µV; V id =13/200,000=65µV; V id

159. Example Why practically Vo=13V? In the Lab set up, it is difficult to measure 65µV; Leakage current in test setup, Noise induced can easily generate 1000µV Due to internal imbalance in op-amp circuits a small voltage that may exceed V id , max is available at i /p terminals of op-amp; Hence Op-amp are used as voltage comparators in Open loop

160. Hence Op-amp are used as voltage comparators in Open loop Open loop applications- OP-AMP

161. V OLTAGE F OLLOWER The output voltage “follows” the input voltage (gain is unity) v o 180 v i v o = v i

162. Voltage Follower Why to use a amplifier with gain unity? Op-amp internal resistance is very high; It draws negligible current from the source; Avoid loading effect

163. V OLTAGE F OLLOWER A voltage follower or “ buffer” or “ Isolation amplifier” circuit provides a means of isolating an input signal from a load by using a stage having unity voltage gain. It offers no phase or polarity inversion, and act as an ideal circuit with very high input impedance and low output impedance . SOURCE High output impedance LOAD Low input impedance Buffer Isolates Loading Effects i ~ 182 i L

164. E XAMPLE N UMERICAL Problem: What is the power absorbed by the 4-kΩ resistor below? Ans: Current through 4-kΩ resistor is i = 6/(4 + 2) = 1 mA => Power absorbed = i 2 R = (10 -3 ) 2 × (4000) W = 4 mW 183

165. S UMMING A MPLIFIER A summing amplifier is an op-amp circuit that combines several inputs and produces an output that is the weighted sum of the inputs. v o R f R a v v i f i b i a R b i c R c v a v b v c i 1 f f f o a b b R R R R R  v  v   v  v   R c   a c  184

166. S UMMING A MPLIFIER Applying KCL at node v , (1) The currents are given by, Using (1), (2) & (3) => i 1  i a  i b  i c a b c a b c a b c R R R v  v v  v v  v (2) i  , i  , i  v o R f R a v v i f i b i a R b i c R c v a v b v c i 1 Also i 1   i f (3) f R a R b R c R v a  v  v b  v  v c  v    v o  v      185

167. S UMMING A MPLIFIER f f f o a b b R R R R R  v  Thus, output is given by v   v  v   R c   a c  v o R f R a v v i f i b i a R b i c R c v a v b v c i 1 R a R b R c R f  v v  v v  v v  v v  a  b  c    o   

168. N UMERICAL E XAMPLE 1 Problem: Calculate the output voltage of an op-amp summing amplifier for the following sets of voltages and resistors. Given, R f = 1 MΩ. (a) V 1 = 1V, V 2 = 2V, V 3 = 3V; R 1 = 500 kΩ, R 2 = 1 MΩ , R 3 = 1 MΩ. (b) V 1 = -2V, V 2 = 3V, V 3 = 1V; R 1 = 200 kΩ , R 2 = 500 kΩ , R 3 = 1 MΩ. 187

169. Soln: Using the summing amplifier formula, V o = -(R f /R 1 )V 1 - (R f /R 2 )V 2 - (R f /R 3 )V 3 (a) (b) o v    1 M *1  1 M *2  1 M *3    7 V   500 k 1 M 1 M   o v    1 M *   2   1 M *3  1 M *1   3 V   200 k 500 k 1 M   188

170. N UMERICAL E XAMPLE 2 Problem: Find an expression for the output voltage v o below. Assume an ideal op-amp. What mathematical operation does the circuit perform? 189 NON- INVERTING SUMMING AMPLIFIER: A summer that gives non inverted sum.

171. A PPLICATION OF S UMMING A MPLIFIER Digital-to-Analog Converter (DAC) Accepts inputs of digital/binary values at, typically, 0-V (for bit ‘0’) or V ref (for bit ‘ 1’) and provides an output vol t age pr o portion a l to the decimal equivalent of the input binary value. E.g. consider a DAC with digital data of 4-bits R 4 = 2 R 3 = 4 R 2 = 8 R 1 (in general, R n = 2 n-1 R 1 for n-bits) 1 2 3 2 3 f f f f o R V R R R R R R   V   V  V  V   R 4   1 4  191

172. N UMERICAL E XAMPLE Problem: In the DAC circuit below, R f = 10 kΩ, R 1 = 10 kΩ, R 2 = 20 kΩ, R 3 = 40 kΩ, and R 4 = 80 kΩ. Obtain the analog output voltage for the digital inputs [0000], [0001], [0010], . . . , [1111]. Consider V ref = 1 V. 192

173. Soln : Thus, a digital input [ V 1 V 2 V 3 V 4 ] = [0000] produces an analog output V o = 0V and input [ V 1 V 2 V 3 V 4 ] = [0001] gives V o = -0.125 V. Similarly, [ V 1 V 2 V 3 V 4 ] = [0010] ⇒ V o = -0.25 V [ V 1 V 2 V 3 V 4 ] = [0011] ⇒ V o = -(0.25 + 0.125) = -0.375 V [ V 1 V 2 V 3 V 4 ] = [0100] ⇒ V o = -0.5 V [ V 1 V 2 V 3 V 4 ] = [1111] ⇒ V o = -(1 + 0.5 + 0.25 + 0.125) = -1.875 V 1 2 3 4 1 2 3 4 f f f f o R R R R V =>  V o  V 1  0.5 V 2  0.25 V 3  0.125 V 4 R R R R  V  V  V  V  193

174. D IFFERENCE A MPLIFIER A difference amplifier is a device that amplifies the difference between two inputs but rejects any signals common to the two inputs. V o R f R a v v i f i c R b R c V b V c v 1 v 2 R 1 R 3 R 2 R 4 v o v v’ 194

175. D IFFERENCE A MPLIFIER Applying KCL at node v, => …(1) => …(2) As v = v’ => (using (1) and (2)) R 1 R 2 v  v v  v 1    o 2 2 1 1 o R R v R   v   1 v   R   1  Applying KCL at node v’, v 2 R 3 R 4  v '  v '  2 v v '  R 4 R 3  R 4 2 2 2 1 1 o R R 4 R v R   v   1 v   R  R  R  1  3 4 V o R f i f 195

176. N UMERICAL E XAMPLE Problem: Design an op-amp circuit with inputs v 1 and v 2 and output v o = -5 v 1 + 3 v 2 Comparing it with the given equation, we have and 1 2 1 3 1 o R R R v   R 1    2  2  Soln: The output f or the di f ference amplifier is v    2 v R   1  R   R 1  R 4  R 2  5 R 1  R 2  5 R 1 6 3 5 R 4   1  R 1 R   5  2   3   5  1  R 3   1  R 3    R 4   197 R 3  R 4 Thus, if we choose R 1 = 10 kΩ and R 3 = 20 kΩ, then R 2 = 50 kΩ and R 4 = 20 kΩ.

177. ADDER CUM SUBTRACTOR It is possible to perform addition and subtraction operation simultaneously using single OP-AMP. 198

178. ADDER CUM SUBTRACTOR Applying Superposition theorem:/Instead Use KCL 199 Similarly

179. ADDER CUM SUBTRACTOR 200

180. Numerical Example- Home Work 1. Find the output voltage

181. D IFFERENTIATOR / DIFFERENTIATION A MPLIFIER KCL at node v => Since v = v’ = 0, i c   i 1  v o C 1 R F v i v v i 1 i c Differentiator circuits are unstable because any fast varying electrical noise within the circuit is exaggerated by the differentiator. 202 O/P is R F C 1 times negative instantaneous rate of change of input voltage w.r.t time. Cosine wave input will produce sine wave as output Triangular wave input will produce square Wave output;

182. I NTEGRATOR A MPLIFIER An integrator amplifier is an op-amp circuit whose output is proportional to the integral of the input signal over time. v o C R 1 v i v v i c i 1 1 t v o   R C  v i ( t ) dt 203

183. I NTEGRATOR A MPLIFIER KCL at node v => The currents can be written as => Integrating from time 0 to t , i 1   i c 1 i o , C R d t v  v dv i  i c   v o C 1 v i v v i c i 1 R v i  v   C dv o R dt o i RC => dv   1 v dt 1 t v o ( t )  v o ( )   R C  v i (t) dt It is necessary to always discharge the capacitor prior to application => of a signal i.e. v o (0)  c i = 1 t v o   R C  v i ( t) dt 204