Sequential Circuits: Latches and Flip-Flops By Dr. G. S. Virdi Ex-Chief Scientist, CSIR-Central Electronics Engineering Research Institute (CEERI), Pilani – India

This lecture provides an in-depth understanding of sequential logic circuits used in modern digital electronic systems. It explains the principles and operation of memory elements, including SR, D, JK, and T flip-flops, as well as latches with enable and clock control. The content also covers both synchronous and asynchronous sequential circuits, edge-triggering mechanisms, and practical applications in frequency division, data storage, and control systems.

Authored by Dr. G. S. Virdi, Ex-Chief Scientist at CSIR-CEERI Pilani, with extensive R&D experience in micro and digital electronics device technology, this lecture is specially prepared for graduate students, engineering professionals, and researchers. It will be uploaded on SlideShare for academic and industrial benefit.

1. 1
Sequential Circuit
Dr.G.S.Virdi
Ex.Chief Scientist
CSIR -Central Electronics Engineering Research Institute
Pilani -333031,India

2. Contents
2
Introduction
MemoryElement
Latch



SRlatch
Dlatch
Flip-flop



SRflip-flop
Dflip-flop
JKflip-flop
T flip-flop
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3. Introduction
3
Sequentialcircuitconsistsoffeedbackpathand
severalmemoryelements
Sequentialcircuit=CombinationalLogic+
MemoryElements
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4. Introduction
4
Therearetwotypesofsequentialcircuit
Synchronous–outputchangeatcertaintime
Asynchronous–outputchangeanytime
Multivibrator–sequentialcircuitcategory–can
be


Bistable–consistoftwostablecondition
Monostable–consistofonestablecondition
Astable- nostablecondition


Bistablelogicdeviceislatchandflip-flop
Latchandflip-flopdifferbythemethodusedto
changestablecondition
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5. MemoryElement
Memoryelementdevicethatcanremembera value
foracertainperiod,orchangevaluebased onthe
inputinstruction
Example:Latchandflip-flop
5
Commandsforlatchesincludesetandreset
commands
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6. 6
Flip-flopisamemoryelementwhichchangeits
condition basedonclocksignal
Clockisasquare
waveform
MemoryElement
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7. MemoryElement
7
Therearetwotypesoftrigger/activator
Pulsetriggered
Edgetriggered
Pulsetriggered

Latch
ON=1,
OFF=0
Edgetriggered


Flip-flop
Positiveedgetriggered(ON=when0to1,OFF=othertime)
Negativeedgetriggered(ON=when1to0,OFF=othertime)
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8. SRLatch
8
Outputhascomplement:QandQ’
WhenQHIGH,latchinSET
condition WhenQLOW,latchin
RESETcondition
ForSRwithactivehighinput(alsoknownasNORgate
latch)
R=HIGH(andS=LOW)–RESET
condition S=HIGH(andR=LOW)–SET
condition BothLOW–noconditionchange
BothHIGH-QandQ’becomesLOW(invalid)
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9. SRLatch
9
ForallS’R’withactiveLOWinput(alsoknownasNAND
gatelatch)
R=LOW(andS=HIGH)–RESE
condition S=LOW(andR=HIGH)–SET
condition BothHIGH–noconditionchange
BothLOW-QandQ’becomesHIGH(invalid)
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10. SRLatch
10
SRwithactiveHIGHinput
S’R’withactiveLOWinput
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11. SRLatch
11
SRwithactiveHIGHinput
S’R’withactiveLOWinput
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12. SRLatchwithGate
12
SRlatch+enable(EN)inputamd2NANDgate
-SRLatchwithGate
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13. 13


Outputchange(ifneeded)onlywhenENatHIGH
condition
Whichconditionisinvalid?
CriteriaTable
SRLatchwithGate
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14. DLatchwithGate
14
MakeinputRthesameasS’-DLatchwithGate
DlatcheliminateinvalidconditioninSRlatch
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15. DLatchwithGate
15
WhenENisHIGH
D=HIGH–latchisinSET
D=LOW–latchisinRESET
Therefore,whenENisHIGH,Qwillfollow
inputD CriteriaTable:
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16. EdgeTriggeredFlip-flop
16

Flip-flop–bistablesynchronousdevice
Outputchangeitsconditionatcertainpointoninput
triggernamedclock
Conditionchangeeitheratpositiveedge(upedge)
oratnegativeedge(downedge)ofclocksignal
clocksignal
PositiveEdge NegativeEdge
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17. 17
flip-flopSR,DandJKedgetriggeredismarkedwith
“>”symbolatclockinput
Positiveedgetriggeredflip-flop
Negativeedgetriggeredflip-flop
SRFlip-flop
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18. SRFlip-flop
18
SRflip-flop,atedgetriggeredclockpulse
S=HIGH(andR=LOW)–SET
condition R=HIGH(andS=LOW)
BothinputHIGH-invalid
RESETcondition BothinputLOW–no
change
CriteriatableofedgetriggeredSRflip-flop
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19. SRFlip-flop
19
Itconsistofthreeparts


NANDlatch
Pulsesteeringcircuit
Pulsetransactioncircuitdetector(oredge
detector)
Pulsetransactiondetectorcircuitwilldetectuptrigger
(ordown)andproduceveryshortdurationspike
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20. SRFlip-flop
20
Pulsetransactiondetector
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21. DFlip-flop
21
Dflip-flop:oneinputD(data)
D=HIGH–SETcondition
D=LOW–RESETcondition
QwillfollowDatclockedge
TochangeSRflip-floptoDflip-flop:addinverter
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22. DFlip-flop
22
Usage:Paralleldatatransaction
TotransferlogicaloutputcircuitX,Y,ZtoQ
1,Q
2,and
Q
3tobestored
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23. JKFlip-flop
23
Thereisnoinvalidcondition
Thereistogglecondition
J=HIGH(andK=LOW)–SETcondition
K=HIGH(andJ=LOW)–RESETcondition
BothinputLOW–nochange
BothinputHIGH–“toggle”
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24. JKFlip-flop
24
JKFlip-flop
CriteriaTable
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25. TFlip-flop
25
Tflip-flopsingleinputversionforJKflip-flop,
formedbycombiningJKinput
CriteriaTable
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26. TFlip-flop
26
Usage:Asfrequencydivider
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27. 27
Synchronous & Asynchronous Inputs of Flip-Flops
✅Synchronous Inputs (SR, D, JK)
Input data is transferred to output only on the triggering
edge of the clock pulse.
Output changes are fully controlled by the clock.
✅Asynchronous Inputs (PRE & CLR / SD & RD)
Output can change independent of the clock pulse.
These inputs directly force the flip-flop output.
Asynchronous Input Actions
PRE = HIGH → Q becomes HIGH immediately
CLR = HIGH → Q becomes LOW immediately
Normal flip-flop operation occurs when both PRE and
CLR are LOW
AsynchronousInput

28. AsynchronousInput
28
JKflip-flopwithactiveLOWpresetandclear
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29. MasterSlaveFlip-flop
29

Masterisactivatedwhenpositiveedgeand Slaveis
activatedwhenclocknegativeedge triggered
MasterSlaveFlip-flop
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