Sequential Logic Design_____________.ppt
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About This Presentation
Sequential Logic Design
Slide Content
1Copyright © 2013 Elsevier Inc. All rights reserved.
Chapter 3
Sequential Logic Design
Chapter 3
Sequential Logic Design
2Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.1 Cross-coupled inverter pair
Figure 3.1 Cross-coupled inverter pair
3Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.2 Bistable operation of cross-coupled inverters
Figure 3.2 Bistable operation of cross-coupled inverters
4Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.3 SR latch schematic
Figure 3.3 SR latch schematic
5Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.4 Bistable states of SR latch
Figure 3.4 Bistable states of SR latch
6Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.5 SR latch truth table
Figure 3.5 SR latch truth table
7Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.6 SR latch symbol
Figure 3.6 SR latch symbol
8Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.7 D latch: (a) schematic, (b) truth table, (c) symbol
Figure 3.7 D latch: (a) schematic, (b) truth table, (c) symbol
9Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.8 D flip-flop: (a) schematic, (b) symbol, (c) condensed symbol
Figure 3.8 D flip-flop: (a) schematic, (b) symbol, (c) condensed symbol
10Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.9 A 4-bit register: (a) schematic and (b) symbol
Figure 3.9 A 4-bit register: (a) schematic and (b) symbol
11Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.10 Enabled flip-flop: (a, b) schematics, (c) symbol
Figure 3.10 Enabled flip-flop: (a, b) schematics, (c) symbol
12Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.11 Synchronously resettable flip-flop: (a) schematic, (b, c)
symbols
Figure 3.11 Synchronously resettable flip-flop: (a) schematic, (b, c)
symbols
13Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.12 D latch schematic
Figure 3.12 D latch schematic
14Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.13 D flip-flop schematic
Figure 3.13 D flip-flop schematic
15Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.14 Example waveforms
Figure 3.14 Example waveforms
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Figure 3.15 Solution waveforms
Figure 3.15 Solution waveforms
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Figure 3.16 Three-inverter loop
Figure 3.16 Three-inverter loop
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Figure 3.17 Ring oscillator waveforms
Figure 3.17 Ring oscillator waveforms
19Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.18 An improved (?) D latch
Figure 3.18 An improved (?) D latch
20Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.19 Latch waveforms illustrating race condition
Figure 3.19 Latch waveforms illustrating race condition
21Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.20 Flip-flop current state and next state
Figure 3.20 Flip-flop current state and next state
22Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.21 Example circuits
Figure 3.21 Example circuits
23Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.22 Finite state machines: (a) Moore machine, (b) Mealy
machine
Figure 3.22 Finite state machines: (a) Moore machine, (b) Mealy
machine
24Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.23 Campus map
Figure 3.23 Campus map
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Figure 3.24 Black box view of finite state machine
Figure 3.24 Black box view of finite state machine
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Figure 3.25 State transition diagram
Figure 3.25 State transition diagram
27Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.26 State machine circuit for traffic light controller
Figure 3.26 State machine circuit for traffic light controller
28Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.27 Timing diagram for traffic light controller
Figure 3.27 Timing diagram for traffic light controller
29Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.28 Divide-by-3 counter (a) waveform and (b) state transition diagram
Figure 3.28 Divide-by-3 counter (a) waveform and (b) state transition diagram
30Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.29 Divide-by-3 circuits for (a) binary and (b) one-hot encodings
Figure 3.29 Divide-by-3 circuits for (a) binary and (b) one-hot encodings
31Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.30 FSM state transition diagrams: (a) Moore machine, (b) Mealy machine
Figure 3.30 FSM state transition diagrams: (a) Moore machine, (b) Mealy machine
32Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.31 FSM schematics for (a) Moore and (b) Mealy machines
Figure 3.31 FSM schematics for (a) Moore and (b) Mealy machines
33Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.32 Timing diagrams for Moore and Mealy machines
Figure 3.32 Timing diagrams for Moore and Mealy machines
34Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.33 (a) single and (b) factored designs for modified
traffic light controller FSM
Figure 3.33 (a) single and (b) factored designs for modified
traffic light controller FSM
35Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.34 State transition diagrams: (a) unfactored, (b) factored
Figure 3.34 State transition diagrams: (a) unfactored, (b) factored
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Figure 3.35 Circuit of found FSM for Example 3.9
Figure 3.35 Circuit of found FSM for Example 3.9
37Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.36 State transition diagram of found FSM from Example 3.9
Figure 3.36 State transition diagram of found FSM from Example 3.9
38Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.37 Timing specification for synchronous sequential circuit
Figure 3.37 Timing specification for synchronous sequential circuit
39Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.38 Path between registers and timing diagram
Figure 3.38 Path between registers and timing diagram
40Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.39 Maximum delay for setup time constraint
Figure 3.39 Maximum delay for setup time constraint
41Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.40 Minimum delay for hold time constraint
Figure 3.40 Minimum delay for hold time constraint
42Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.41 Back-to-back flip-flops
Figure 3.41 Back-to-back flip-flops
43Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.42 Sample circuit for timing analysis
Figure 3.42 Sample circuit for timing analysis
44Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.43 Timing diagram: (a) general case, (b) critical path, (c) short path
Figure 3.43 Timing diagram: (a) general case, (b) critical path, (c) short path
45Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.44 Corrected circuit to fix hold time problem
Figure 3.44 Corrected circuit to fix hold time problem
46Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.45 Timing diagram with buffers to fix hold time problem
Figure 3.45 Timing diagram with buffers to fix hold time problem
47Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.46 Clock skew caused by wire delay
Figure 3.46 Clock skew caused by wire delay
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Figure 3.47 Timing diagram with clock skew
Figure 3.47 Timing diagram with clock skew
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Figure 3.48 Setup time constraint with clock skew
Figure 3.48 Setup time constraint with clock skew
50Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.49 Hold time constraint with clock skew
Figure 3.49 Hold time constraint with clock skew
51Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.50 Input changing before, after, or during aperture
Figure 3.50 Input changing before, after, or during aperture
52Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.51 Stable and metastable states
Figure 3.51 Stable and metastable states
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Figure 3.52 Synchronizer symbol
Figure 3.52 Synchronizer symbol
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Figure 3.53 Simple synchronizer
Figure 3.53 Simple synchronizer
55Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.54 Input timing
Figure 3.54 Input timing
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Figure 3.55 Circuit model of bistable device
Figure 3.55 Circuit model of bistable device
57Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.56 Resolution trajectories
Figure 3.56 Resolution trajectories
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Figure 3.57 Spatial and temporal parallelism in the cookie kitchen
Figure 3.57 Spatial and temporal parallelism in the cookie kitchen
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Figure 3.58 Circuit with no pipelining
Figure 3.58 Circuit with no pipelining
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Figure 3.59 Circuit with two-stage pipeline
Figure 3.59 Circuit with two-stage pipeline
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Figure 3.60 Circuit with three-stage pipeline
Figure 3.60 Circuit with three-stage pipeline
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Figure 3.61 Input waveforms of SR latch for Exercise 3.1
Figure 3.61 Input waveforms of SR latch for Exercise 3.1
63Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.62 Input waveforms of SR latch for Exercise 3.2
Figure 3.62 Input waveforms of SR latch for Exercise 3.2
64Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.63 Input waveforms of D latch or flip-flop for Exercises 3.3 and 3.5
Figure 3.63 Input waveforms of D latch or flip-flop for Exercises 3.3 and 3.5
65Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.64 Input waveforms of D latch or flip-flop for Exercises 3.4 and 3.6
Figure 3.64 Input waveforms of D latch or flip-flop for Exercises 3.4 and 3.6
66Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.65 Mystery circuit
Figure 3.65 Mystery circuit
67Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.66 Mystery circuit
Figure 3.66 Mystery circuit
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Figure 3.67 Muller C-element
Figure 3.67 Muller C-element
69Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.68 Circuits
Figure 3.68 Circuits
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Figure 3.69 State transition diagram
Figure 3.69 State transition diagram
71Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.70 State transition diagram
Figure 3.70 State transition diagram
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Figure 3.71 FSM input waveforms
Figure 3.71 FSM input waveforms
73Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.72 FSM schematic
Figure 3.72 FSM schematic
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Figure 3.73 FSM schematic
Figure 3.73 FSM schematic
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Figure 3.74 Registered four-input XOR circuit
Figure 3.74 Registered four-input XOR circuit
76Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.75 2-bit adder schematic
Figure 3.75 2-bit adder schematic
77Copyright © 2013 Elsevier Inc. All rights reserved.
Figure 3.76 New and improved synchronizer
Figure 3.76 New and improved synchronizer
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Figure 3.77 Signal waveforms
Figure 3.77 Signal waveforms
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Figure M 01
Figure M 01
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Figure M 02
Figure M 02
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Figure M 03
Figure M 03
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Figure M 04
Figure M 04
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Figure M 05
Figure M 05
84Copyright © 2013 Elsevier Inc. All rights reserved.
UNN Figure 1
UNN Figure 1
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