Snake Game on FPGA in Verilog

Xilinx Zybo Zynq 7000

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A Miniproject Report on
SNAKE GAME
USING FPGA

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ABSTRACT
Snake is the common name for a videogame concept where the player maneuvers a line which grows in length,
with the line itself being a primary obstacle. The concept originated in the 1976 arcade game Blockade, and
the ease of implementing Snake has led to hundreds of versions for many platforms.
The player controls a dot, square, or object on a bordered plane. As it moves forward, it leaves a trail behind,
resembling a moving snake. In some games, the end of the trail is in a fixed position, so the snake continually
gets longer as it moves. In another common scheme, the snake has a specific length, so there is a moving tail
a fixed number of units away from the head. The player loses when the snake runs into the screen border, a
trail or other obstacle, or itself.

Final version of Snake game
This report describes the successful implementation of Snake game on a Xilinx Zybo Zynq – 7000 FPGA kit
and a VGA monitor. The game logic is written in Verilog and the hardware is described in Verilog HDL. The
game layout is shown above.

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CONTENTS

Page
No
 Aim…………………………………………………………………………………………. 4

 Design and Description…………………………………………………………………… 4

 Schematic………………………………………………………………….……………… 6

 Verilog Code……………………………………………………………………………… 7

 Constraint File…………………………………………………………………………… 11

 Simulation Waveform…………………………………………………………………… 12

 Implemented Design……………………………………………………...……………… 12
 Implemented Schematic…………………………………………………………………… 13
 Synthesis Report………………………………………………………….……………… 13
 Conclusion………………………………………………………………...……………… 16
 References………………………………………………………………………………… 16

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AIM
To design a video graphic Snake game using Verilog hardware description and implementing it using Xilinx
Zybo Zynq - 7000 FPGA kit.
DESIGN AND DESCRIPTION


Fig 1: FPGA – VGA monitor interface
COMPONENTS AND TOOLS USED
 Xilinx Zybo Zynq – 7000
 VGA monitor
 Xilinx Vivado 2017.2
a) Xilinx Zybo Zynq – 7000
The ZYBO Zynq Board) is a feature-rich, ready-to-use, entry-level embedded software and digital circuit
development platform built around the smallest member of the Xilinx Zynq-7000 family, the Z-7010. The Z-
7010 is based on the Xilinx All Programmable System-on-Chip (AP SoC) architecture, which tightly
integrates a dual-core ARM Cortex-A9 processor with Xilinx 7-series Field Programmable Gate Array
(FPGA) logic. When coupled with the rich set of multimedia and connectivity peripherals available on the
ZYBO, the Zynq Z-7010 can host a whole system design. The on-board memories, video and audio I/O, dual-
role USB, Ethernet, and SD slot will have your design up-and-ready with no additional hardware needed.
Additionally, six Pmod ports are available to put any design on an easy growth path.

Fig 2: Xilinx Zybo Zynq – 7000 FPGA kit

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b) VGA Monitor
CRT-based VGA displays use amplitude-modulated moving electron beams (or cathode rays) to display
information on a phosphor-coated screen. LCD displays use an array of switches that can impose a voltage
across a small amount of liquid crystal, thereby changing light permittivity through the crystal on a pixel-by-
pixel basis. Although the following description is limited to CRT displays, LCD displays have evolved to use
the same signal timings as CRT displays (so the “signals” discussion below pertains to both CRTs and LCDs).
Color CRT displays use three electron beams (one for red, one for blue, and one for green) to energize the
phosphor that coats the inner side of the display end of a cathode ray tube.

Fig 3: Colour CRT Display Fig 4: VGA horizontal synchronization
A VGA controller circuit must generate the HS and VS timings signals and coordinate the delivery of video
data based on the pixel clock. The pixel clock defines the time available to display one pixel of information.
The VS signal defines the “refresh” frequency of the display, or the frequency at which all information on the
display is redrawn. The minimum refresh frequency is a function of the display’s phosphor and electron beam
intensity, with practical refresh frequencies falling in the 50Hz to 120Hz range. The number of lines to be
displayed at a given refresh frequency defines the horizontal “retrace” frequency. For a 640-pixel by 480-row
display using a 25MHz pixel clock and 60 +/-1Hz refresh, the signal timings shown in Fig. 11 can be derived.
Timings for sync pulse width and front and back porch intervals (porch intervals are the pre- and post-sync
pulse times during which information cannot be displayed) are based on observations taken from actual VGA
displays.

Figure 5: Signal timings for a 640-pixel by 480 row display using a 25MHz pixel clock and 60Hz vertical refresh.

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c) Xilinx Vivado 2017.2

Fig 7: Xilinx Vivado 2017.2
Vivado Design Suite is a software suite produced by Xilinx for synthesis and analysis of HDL designs,
superseding Xilinx ISE with additional features for system on a chip development and high-level synthesis.
Vivado enables developers to synthesize (compile) their designs, perform timing analysis,
examine RTL diagrams, simulate a design's reaction to different stimuli, and configure the target device with
the programmer.
SCHEMATIC

Fig 8: Snake game RTL schematic

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VERILOG CODE
MAIN MODULE
module Snake (red,green,blue,h_sync,v_sync,clk,reset,l,r,u,d);

input clk, reset, l, r, u, d;
output reg [4:0] red, blue;
output reg [5:0] green;
output h_sync, v_sync;

wire VGA_clk,update_clock,displayArea;
wire[9:0] xCount;
wire[9:0] yCount;
wire [3:0] direction;
wire [9:0] randX;
wire [9:0] randomX;
wire [8:0] randY;
wire [8:0] randomY;
reg apple;
reg border;
wire R,G,B;
reg snake;
reg gameOver;
reg head;
reg [9:0] appleX;
reg [9:0] appleY;
reg inX, inY;
reg [9:0] snakeX;
reg [8:0] snakeY;

ClockDivider divider (clk, VGA_clk);
UpdateClock upd(clk,update_clock);
VGAgenerator vga(VGA_clk, xCount, yCount, displayArea, h_sync, v_sync);
Random ran(VGA_clk,randX,randY);
ButtonInput but(clk,l,r,u,d,direction);

assign randomX = randX;
assign randomY = randY;

initial
begin
snakeX = 10'd20;
snakeY = 9'd20;
end

always @(posedge VGA_clk)
begin
inX <= (xCount > appleX & xCount < (appleX + 50));
inY <= (yCount > appleY & yCount < (appleY + 50));
apple <= inX & inY;
end

always@(posedge VGA_clk)
begin
border <= ((((xCount >= 0) & (xCount < 15) & ((yCount >= 220) & (yCount < 280))) |
(xCount >= 630) & (xCount < 641) &
((~yCount >= 220) & (~yCount < 280))) | ((yCount >= 0) & (yCount < 15) |
(yCount >= 465) & (yCount < 481)));
end

always@(posedge VGA_clk)
begin
if(reset | gameOver)
begin
appleX = 350;
appleY = 300;

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end
if(apple & head)
begin
appleX <= randX;
appleY <= randY;
end
end

always@(posedge update_clock)
begin
if(direction == 4'b0001) begin snakeX = snakeX - 5; end
else if (direction == 4'b0010 ) begin snakeX = snakeX + 5; end
else if (direction == 4'b0100) begin snakeY = snakeY - 5; end
else if(direction == 4'b1000) begin snakeY = snakeY + 5; end
end

always@(posedge VGA_clk)
begin
head <= (xCount > snakeX & xCount < (snakeX+10)) & (yCount > snakeY & yCount <
(snakeY+10));
end

always @(posedge VGA_clk)
begin
if((border & (head)) | reset) gameOver<=1;
else gameOver<=0;
end

assign R = (displayArea & (apple));
assign G = (displayArea & (head));
assign B = (displayArea & (border));

always@(posedge VGA_clk)
begin
red = {5{R}};
green = {6{G}};
blue = {5{B}};
end

endmodule

CLOCK DIVIDER – 25MHz
module ClockDivider(clk,VGA_clk);
output reg VGA_clk;
input clk;

integer check = 4;
integer a = 0;

always@(posedge clk)
begin
if(a<check)
begin
a <= a + 1;
VGA_clk <= 0;
end
else
begin
a <= 0;
VGA_clk <= 1;
end
end

endmodule

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CLOCK DIVIDER – 25Hz
module UpdateClock (clk,update_clk);
output reg update_clk;
input clk;

reg [21:0] check;

always @ (posedge clk)
begin
if(check < 4000000)
begin
check <= check + 1;
update_clk <= 0;
end
else
begin
check <= 0;
update_clk <= 1;
end
end

endmodule

VGA GENERATOR
module VGAgenerator(VGA_clk, xCount, yCount, displayArea, VGA_hSync, VGA_vSync);
input VGA_clk;
output reg [9:0] xCount, yCount;
output reg displayArea;
output VGA_hSync, VGA_vSync;

reg p_hSync, p_vSync;

integer porchHF = 640; //start of horizontal front porch
integer syncH = 656;//start of horizontal sync
integer porchHB = 752; //start of horizontal back porch
integer maxH = 800; //total length of line.

integer porchVF = 480; //start of vertical front porch
integer syncV = 490; //start of vertical sync
integer porchVB = 492; //start of vertical back porch
integer maxV = 525; //total rows.

always@(posedge VGA_clk)
begin
if(xCount == maxH)
xCount <= 0;
else
xCount <= xCount + 1'b1;
end

always@(posedge VGA_clk)
begin
if(xCount == maxH)
begin
if(yCount == maxV)
yCount <= 0;
else
yCount <= yCount + 1'b1;
end
end

always@(posedge VGA_clk)
begin
displayArea <= ((xCount < porchHF) && (yCount < porchVF));
end

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always@(posedge VGA_clk)
begin
p_hSync <= ((xCount >= syncH) && (xCount < porchHB));
p_vSync <= ((yCount >= syncV) && (yCount < porchVB));
end

assign VGA_vSync = ~p_vSync;
assign VGA_hSync = ~p_hSync;

endmodule

RANDOM POINT
module Random(VGA_clk,randX,randY);
input VGA_clk;
output reg [9:0]randX;
output reg [8:0]randY;


reg [9:0] i=0;
reg [9:0] j = 450;

always @ (posedge VGA_clk)
begin
if (i<610)
i <= i+1'b1;
else
i <= 10'b0;
end

always @ (posedge VGA_clk)
begin
if (j>0)
j <= j-1'b1;
else
j <= 10'd480;
end

always @ (i,j)
begin
randX <= i;
randY <= j;
end

endmodule

BUTTON INPUT
module ButtonInput(clk,l,r,u,d,direction);
input clk,l,r,u,d;
output reg [3:0] direction;

always@(posedge clk)
begin
if(l == 1) begin
direction <= 4'b0001; //left
end
else if(r == 1) begin
direction <= 4'b0010; //right
end
else if(u == 1) begin
direction <= 4'b0100; //up
end
else if(d == 1) begin
direction <=4'b1000; //down
end

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else begin
direction <= direction; //keep last input
end
end

endmodule
CONSTRIANT FILE
##Clock signal
set_property -dict { PACKAGE_PIN L16 IOSTANDARD LVCMOS33 } [get_ports { clk }];
#IO_L11P_T1_SRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { clk }];

##Buttons
set_property -dict { PACKAGE_PIN R18 IOSTANDARD LVCMOS33 } [get_ports { l }];
#IO_L20N_T3_34 Sch=BTN0
set_property -dict { PACKAGE_PIN P16 IOSTANDARD LVCMOS33 } [get_ports { r }];
#IO_L24N_T3_34 Sch=BTN1
set_property -dict { PACKAGE_PIN V16 IOSTANDARD LVCMOS33 } [get_ports { u }];
#IO_L18P_T2_34 Sch=BTN2
set_property -dict { PACKAGE_PIN Y16 IOSTANDARD LVCMOS33 } [get_ports { d }];
#IO_L7P_T1_34 Sch=BTN3

##VGA Connector
set_property -dict { PACKAGE_PIN M19 IOSTANDARD LVCMOS33 } [get_ports { red[0] }];
#IO_L7P_T1_AD2P_35 Sch=VGA_R1
set_property -dict { PACKAGE_PIN L20 IOSTANDARD LVCMOS33 } [get_ports { red[1] }];
#IO_L9N_T1_DQS_AD3N_35 Sch=VGA_R2
set_property -dict { PACKAGE_PIN J20 IOSTANDARD LVCMOS33 } [get_ports { red[2] }];
#IO_L17P_T2_AD5P_35 Sch=VGA_R3
set_property -dict { PACKAGE_PIN G20 IOSTANDARD LVCMOS33 } [get_ports { red[3] }];
#IO_L18N_T2_AD13N_35 Sch=VGA_R4
set_property -dict { PACKAGE_PIN F19 IOSTANDARD LVCMOS33 } [get_ports { red[4] }];
#IO_L15P_T2_DQS_AD12P_35 Sch=VGA_R5
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { green[0] }];
#IO_L14N_T2_AD4N_SRCC_35 Sch=VGA_G0
set_property -dict { PACKAGE_PIN N20 IOSTANDARD LVCMOS33 } [get_ports { green[1] }];
#IO_L14P_T2_SRCC_34 Sch=VGA_G1
set_property -dict { PACKAGE_PIN L19 IOSTANDARD LVCMOS33 } [get_ports { green[2] }];
#IO_L9P_T1_DQS_AD3P_35 Sch=VGA_G2
set_property -dict { PACKAGE_PIN J19 IOSTANDARD LVCMOS33 } [get_ports { green[3] }];
#IO_L10N_T1_AD11N_35 Sch=VGA_G3
set_property -dict { PACKAGE_PIN H20 IOSTANDARD LVCMOS33 } [get_ports { green[4] }];
#IO_L17N_T2_AD5N_35 Sch=VGA_G4
set_property -dict { PACKAGE_PIN F20 IOSTANDARD LVCMOS33 } [get_ports { green[5] }];
#IO_L15N_T2_DQS_AD12N_35 Sch=VGA=G5
set_property -dict { PACKAGE_PIN P20 IOSTANDARD LVCMOS33 } [get_ports { blue[0] }];
#IO_L14N_T2_SRCC_34 Sch=VGA_B1
set_property -dict { PACKAGE_PIN M20 IOSTANDARD LVCMOS33 } [get_ports { blue[1] }];
#IO_L7N_T1_AD2N_35 Sch=VGA_B2
set_property -dict { PACKAGE_PIN K19 IOSTANDARD LVCMOS33 } [get_ports { blue[2] }];
#IO_L10P_T1_AD11P_35 Sch=VGA_B3
set_property -dict { PACKAGE_PIN J18 IOSTANDARD LVCMOS33 } [get_ports { blue[3] }];
#IO_L14P_T2_AD4P_SRCC_35 Sch=VGA_B4
set_property -dict { PACKAGE_PIN G19 IOSTANDARD LVCMOS33 } [get_ports { blue[4] }];
#IO_L18P_T2_AD13P_35 Sch=VGA_B5
set_property -dict { PACKAGE_PIN P19 IOSTANDARD LVCMOS33 } [get_ports h_sync];
#IO_L13N_T2_MRCC_34 Sch=VGA_HS
set_property -dict { PACKAGE_PIN R19 IOSTANDARD LVCMOS33 } [get_ports v_sync];
#IO_0_34 Sch=VGA_VS

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TEST BENCH
module test_snake();
reg clk,reset,l,r,u,d;
wire VGA_clk,update_clock;
wire red,green,blue,h_sync,v_sync;

Snake test(red,green,blue,h_sync,v_sync,clk,reset,l,r,u,d);

always
#1 clk = ~clk;

assign VGA_clk = test.VGA_clk;
assign update_clock = test.update_clock;

initial
begin
clk = 0; reset = 0;
l = 1; r = 0; u = 0; d = 0; #30;
l = 0; r = 1; u = 0; d = 0; #30;
l = 0; r = 0; u = 1; d = 0; #30;
l = 0; r = 0; u = 0; d = 1; #30;
$finish;
end

endmodule

SIMULATION WAVEFORM

Fig 9: Simulation waveform of the code
IMPLEMENTED DESIGN

Fig 10: Implemented design

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IMPLEMENTED SCHEMATIC

Fig 11: Implemented schematic
SYNTHESIS REPORT
Start RTL Component Statistics
---------------------------------------------------------------------------------
Detailed RTL Component Info :
+---Adders :
3 Input 12 Bit Adders := 3
3 Input 11 Bit Adders := 1
2 Input 10 Bit Adders := 5
2 Input 9 Bit Adders := 1
+---Registers :
10 Bit Registers := 6
9 Bit Registers := 2
6 Bit Registers := 1
5 Bit Registers := 2
4 Bit Registers := 1
1 Bit Registers := 11
+---Muxes :
2 Input 10 Bit Muxes := 1
2 Input 9 Bit Muxes : = 1
4 Input 4 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
2 Input 1 Bit Muxes := 6
5 Input 1 Bit Muxes := 1
3 Input 1 Bit Muxes := 1
---------------------------------------------------------------------------------
Finished RTL Component Statistics
---------------------------------------------------------------------------------





Start RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------

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Hierarchical RTL Component report
Module Snake
Detailed RTL Component Info :
+---Adders :
3 Input 12 Bit Adders := 3
3 Input 11 Bit Adders := 1
2 Input 10 Bit Adders := 1
2 Input 9 Bit Adders := 1
+---Registers :
10 Bit Registers := 2
9 Bit Registers := 2
6 Bit Registers := 1
5 Bit Registers := 2
1 Bit Registers := 6
+---Muxes :
2 Input 10 Bit Muxes := 1
2 Input 9 Bit Muxes := 1
2 Input 4 Bit Muxes := 2
5 Input 1 Bit Muxes := 1
2 Input 1 Bit Muxes := 2
3 Input 1 Bit Muxes := 1
Module ClockDivider
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module UpdateClock
Detailed RTL Component Info :
+---Registers :
1 Bit Registers := 1
Module VGAgenerator
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 2
+---Registers :
10 Bit Registers := 2
1 Bit Registers := 3
+---Muxes :
2 Input 1 Bit Muxes := 1
Module Random
Detailed RTL Component Info :
+---Adders :
2 Input 10 Bit Adders := 2
+---Registers :
10 Bit Registers := 2
Module ButtonInput
Detailed RTL Component Info :
+---Registers :
4 Bit Registers := 1
+---Muxes :
4 Input 4 Bit Muxes := 1
2 Input 1 Bit Muxes := 3
---------------------------------------------------------------------------------
Finished RTL Hierarchical Component Statistics
---------------------------------------------------------------------------------

Start Part Resource Summary
---------------------------------------------------------------------------------
Part Resources:
DSPs: 80 (col length:40)
BRAMs: 120 (col length : RAMB18 40 RAMB36 20)
---------------------------------------------------------------------------------
Finished Part Resource Summary
---------------------------------------------------------------------------------


Start Writing Synthesis Report

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---------------------------------------------------------------------------------

Report Cell Usage:
+------+-------+------+
| |Cell |Count |
+------+-------+------+
|1 |BUFG | 2|
|2 |CARRY4 | 43|
|3 |LUT1 | 60|
|4 |LUT2 | 79|
|5 |LUT3 | 15|
|6 |LUT4 | 93|
|7 |LUT5 | 31|
|8 |LUT6 | 22|
|9 |FDRE | 135|
|10 |FDSE | 14|
|11 |IBUF | 6|
|12 |OBUF | 18|
+------+-------+------+

Report Instance Areas:
+------+----------+-------------+------+
| |Instance |Module |Cells |
+------+----------+-------------+------+
|1 |top | | 518|
|2 | but |ButtonInput | 27|
|3 | divider |ClockDiv ider | 94|
|4 | ran |Random | 43|
|5 | upd |UpdateClock | 54|
|6 | vga |VGAgenerator | 211|
+------+----------+-------------+------+
---------------------------------------------------------------------------------
Finished Writing Synthesis Report : Time (s): cpu = 00:00:41 ; elapsed = 00:00:44 .
Memory (MB): peak = 651.113 ; gain = 420.867
---------------------------------------------------------------------------------


Fig 12: Utilization report


Fig 13: Power report

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CONCLUSION
As we could see we created a Snake game on FPGA. Our goal was to reproduce one of the most entertaining
games of the computer game history. The Snake game was one of the first electronic games and maybe made
the bases of the computer games history. It was a good choice to create it on FPGA, because we had a suitable
development board which has VGA port for interfacing a computer monitor and push buttons for controls.
Making it on FPGA was a good idea also, because this way we had an embedded system, this way we don’t
have other dependencies not even operating system dependency. We also chose this platform, because this
way we could create an ASIC, a standalone chip, by converting the VHDL code to Verilog with Mentor
Graphic tools and we could create the layout of the chip for the final product. The layout will be made on very
big number layers and as in integrated circuits is done, will be done with auto route. This way we had a game
implemented on a chip, on hardware; this means that we have a standalone device with no speed issues, like
if it would be made in software on a microcontroller.
We plan also to port the project to other platform too, like the ATLYS board, and create the video drivers on
DVI or HDMI interfaces, for newer monitor types and create the keyboard and mouse drivers on USB interface
or even add joystick drivers on USB interface.

REFERENCES
[1] Renuka A. Wasu, Vijay R. Wadhankar, “Design and Implementation of VGA Controller on FPGA”,
International Journal of Innovative Research in Computer and Communication Engineering, Vol. 3, Issue 7,
July 2015.
[2] Fangqin Ying, XiaoqingFeng, “Design and Implementation of VGA Controller Using FPGA”,
International Journal of Advancements in Computing Technology (IJACT), Vol. 4, No. 17, pp. 458-465, Sep
2012.
[2] Ila.Nagarjuna, Pillem. Ramesh, “An FSM Based VGA Controller with 640×480 Resolution”, International
Journal of Engineering and Advanced Technology (IJEAT), Vol. 2, Issue – 4, pp. 881-885, April 2013.
[3] [11] SamirPalnitkar, Verilog HDL: A Guide to Digital Design and Synthesis”, Sun Microsystems, Inc.,
USA, 2003.
[4] “ZYBO™ FPGA Board Reference Manual”, Revised April 11, 2016.