Static Noise margin

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Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit. Noise margin does makes sure that any signal which is logic '1' with finite noise added to it, is still recognised as logic '1' and not logic '0'. It is basically the difference between signal value and the nosie value.

1. Circuit Circuit Ideal Scenario Practical Scenario In In Out Out

2. Circuit Practical Scenario In Out Due to the behavioral aspects of the passive components (R,L,C), the ideal characteristics of the circuits are affected. To understand this behavior, let’s focus on below mentioned terms Noise Margin Switching Activity of CMOS

3. 9/2/2012 3 Noise margin is the amount of noise that a CMOS circuit could withstand without compromising the operation of circuit. Noise margin does makes sure that any signal which is logic '1' with finite noise added to it, is still recognized as logic '1' and not logic '0 '. It is basically the difference between signal value and the noise value Noise Margin

4. 1 Let’s Begin with a example, Consider a Inverter

5. 1 /1 /0 Input and Output of an Inverter

6. 1 /1 /0 Vin Vout I/O Characteristic of a Inverter

7. 1 /1 /0 Vin Vout Vdd Vdd Vdd /2 Ideal I/O Characteristic of a Inverter

8. 1 /1 /0 Vin Vout Vdd Vdd Vdd /2 Infinite Slope Ideal I/O Characteristic of a Inverter with Infinite Slope

9. 1 /1 /0 Vin Vout Vdd Vdd Vdd /2 Infinite Slope Vin Vout Vdd Vdd Vdd /2 Actual I/O Characteristic of a Inverter with Finite Slope

10. 1 /1 /0 Vin Vout Vdd Vdd Vdd /2 Infinite Slope Vin Vout Vdd Vdd Vdd /2 Finite Slope Actual I/O Characteristic of a Inverter with Finite Slope

11. 1 /1 /0 Vin Vout Vdd Vdd Vdd /2 Infinite Slope Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V IL is Input Low Voltage => Any input voltage level between 0 and V IL will be treated as logic ‘0’

12. 1 /1 /0 Vin Vout Vdd Vdd Vdd /2 Infinite Slope Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V O L is Output Low Voltage => Any output voltage level between 0 and V OL will be treated as logic ‘0’

13. 1 /1 /0 Vin Vout Vdd Vdd Vdd /2 Infinite Slope Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V IH is Input High Voltage =>Any input voltage level between V IH and V DD will be treated as logic ‘1’

14. 1 /1 /0 Vin Vout Vdd Vdd Vdd /2 Infinite Slope Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V OH V OH is Output High Voltage =>Any output voltage level between V O H and V DD will be treated as logic ‘1’

15. 1 /1 /0 Vin Vout Vdd Vdd Vdd /2 Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V OH Actual I/O Characteristic of a Inverter

16. 1 /1 /0 Vin Vout Vdd Vdd Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V OH Actual I/O Characteristic of a Inverter

17. 1 /1 /0 Vin Vout Vdd Vdd Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V OH Actual I/O Characteristic of a Inverter

18. 1 /1 /0 Vin Vout Vdd Vdd Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V OH V IL Actual I/O Characteristic of a Inverter

19. 1 /1 /0 Vin Vout Vdd Vdd Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V OH V IL V IH Actual I/O Characteristic of a Inverter

20. 1 /1 /0 Vin Vout Vdd Vdd Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V OH V IL V IH V OL Actual I/O Characteristic of a Inverter

21. 1 /1 /0 Vin Vout Vdd Vdd Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V OH V IL V IH V OL Actual I/O Characteristic of a Inverter V OH

22. 1 /1 /0 Vin Vout Vdd Vdd Vin Vout Vdd Vdd Vdd /2 V IL V IH Finite Slope V OL V OH V IL V IH V OL Slope = -1 Slope = -1 Actual I/O Characteristic of a Inverter V OH

23. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 I/O Characteristic plotted on Scale V OH

24. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 I/O Characteristic plotted on Scale V OH

25. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 Vdd I/O Characteristic plotted on Scale V OH

26. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 Vdd V OH I/O Characteristic plotted on Scale V OH

27. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 Vdd V OH V IH I/O Characteristic plotted on Scale V OH

28. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 Vdd V OH V IH V IL I/O Characteristic plotted on Scale V OH

29. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 Vdd V OH V IH V OL V IL I/O Characteristic plotted on Scale V OH

30. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 Vdd V OH V IH V OL V IL I/O Characteristic plotted on Scale V OH

31. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 Vdd V OH V IH V OL V IL NM H Noise Margin High NM H is the Noise Margin High => Any voltage level in “NM H ” range will be detected as logic ‘1’ V OH

32. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 Vdd V OH V IH V OL V IL NM H Noise Margin High NM L Noise Margin Low V OH NM L is the Noise Margin Low => Any voltage level in “NM L ” range will be detected as logic ‘0’

33. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 Vdd V OH V IH V OL V IL NM H Noise Margin High NM L Noise Margin Low NM H = V OH - V IH NM L = V I L - V O L V OH

34. 1 /1 /0 Vin Vout Vdd Vdd V IL V IH V OL Slope = -1 Slope = -1 Vdd V OH V IH V OL V IL NM H Noise Margin High NM L Noise Margin Low Any Signal in ‘Undefined Region’ will be indefinite logic level V OH Undefined Region

35. Noise Margin Summary 9/2/2012 35 For any signal to be considered as logic ‘0’ and logic ‘1’, it should be in the NM L and NM H ranges, respectively