Stick diagram with EEC 401 Basic VLSI Design.ppt

Stick diagrams vlsi

1. GITAM
(Deemed to be University)
Bengaluru Campus
School of Technology
EEC 401 BASIC VLSI
DESIGN
Presented By
Dr. M. Arun Kumar
Assistant Professor
Department of EECE

2. Module-3
MOS and BiCMOSCircuit Design Process
Contents
MOS layers, stick diagrams, design rules and
layout
CMOS rules
Layout diagrams, symbolic diagrams
Basic Circuit concepts
Sheet resistance
Area capacitance of layers
Delay model
Wiring capacitance
Choice of layers
Scaling of MOS circuits
Scaling models, Scaling function and Limitation of
Scaling

3. 3
MODULE-III
Stick Diagrams
Stick Diagrams

4. 4
PCB Board

5. 5

6. 6

7. 7
Stick Diagrams
N+ N+
Stick Diagrams

8. 8
Stick Diagrams
Gnd
V
DDx x
X
X
X
X
V
DDx x
Gnd
Stick
Diagra
m
Stick Diagrams

9. 9
Stick Diagrams
Gnd
V
DDx x
X
X
X
X
V
DDx x
Gnd
Stick Diagrams

10. 10
Stick Diagrams
VLSI design aims to translate circuit concepts
onto silicon.
stick diagrams are a means of capturing
topography and layer information using
simple diagrams.
Stick diagrams convey layer information
through colour codes (or monochrome
encoding).
Acts as an interface between symbolic circuit
and the actual layout.
Stick Diagrams

11. 11
Stick Diagrams
Does show all components/vias.
It shows relative placement of components.
Goes one step closer to the layout
Helps plan the layout and routing
A stick diagram is a cartoon of a layout.
Stick Diagrams

12. 12
Stick Diagrams
Does notshow
•Exact placement of components
•Transistor sizes
•Wire lengths, wire widths, tub boundaries.
•Any other low level details such as parasitics..
Stick Diagrams

13. 13
Stick Diagrams –Notations
Metal 1
poly
ndiff
pdiff
Can also draw
in shades of
gray/line style.
Stick Diagrams
Similarly for contacts, via, tub etc..

14. 14
Stick Diagrams –Some rules
Rule 1.
When two or more ‘sticks’ of the same type cross
or touch each other that represents electrical
contact.
Stick Diagrams

15. 15
Stick Diagrams –Some rules
Rule 2.
When two or more ‘sticks’ of different type cross
or touch each other there is no electrical contact.
(If electrical contact is needed we have to show the connection
explicitly).
Stick Diagrams

16. 16
Stick Diagrams –Some rules
Rule 3.
When a poly crosses diffusion it represents a
transistor.
Note: If a contact is shown then it is nota transistor.
Stick Diagrams

17. 17
Stick Diagrams –Some rules
Rule 4.
In CMOS a demarcation line is drawn to avoid
touching of p-diff with n-diff. All pMOS must lie
on one side of the line and all nMOS will have
to be on the other side.
Stick Diagrams

18. 18
How to draw Stick Diagrams
Stick Diagrams

19. 19
Stick Diagrams

20. 20
Power
Ground
B
C
OutA
Stick Diagrams

21. Introduction to
CMOS VLSI
Design
MOS devices: static and
dynamic behavior

22. Outline
DC Response
Logic Levels and Noise Margins
Transient Response
Delay Estimation

23. DC Response
DC Response: V
outvs. V
infor a gate
Ex: Inverter
•When V
in= 0 -> V
out= V
DD
•When V
in= V
DD -> V
out= 0
•In between, V
outdepends on
transistor size and current
•By KCL, must settle such that
I
dsn= |I
dsp|
•We could solve equations
•But graphical solution gives more insightI
dsn
I
dsp
V
out
V
DD
V
in

24. Transistor Operation
Current depends on region of transistor behavior
For what V
inand V
outare nMOS and pMOS in
•Cutoff?
•Linear?
•Saturation?

25. nMOS Operation
Cutoff Linear Saturated
V
gsn< V
gsn>
V
dsn<
V
gsn>
V
dsn>I
dsn
I
dsp
V
out
V
DD
V
in

26. nMOS Operation
Cutoff Linear Saturated
V
gsn< V
tn V
gsn> V
tn
V
dsn< V
gsn–V
tn
V
gsn> V
tn
V
dsn> V
gsn–V
tnI
dsn
I
dsp
V
out
V
DD
V
in

27. nMOS Operation
Cutoff Linear Saturated
V
gsn< V
tn V
gsn> V
tn
V
dsn< V
gsn–V
tn
V
gsn> V
tn
V
dsn> V
gsn–V
tnI
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out

28. nMOS Operation
Cutoff Linear Saturated
V
gsn< V
tn
V
in< V
tn
V
gsn> V
tn
V
in> V
tn
V
dsn< V
gsn–V
tn
V
out< V
in-V
tn
V
gsn> V
tn
V
in> V
tn
V
dsn> V
gsn–V
tn
V
out> V
in-V
tnI
dsn
I
dsp
V
out
V
DD
V
in
V
gsn
= V
in
V
dsn
= V
out

29. pMOS Operation
Cutoff Linear Saturated
V
gsp> V
gsp<
V
dsp>
V
gsp<
V
dsp<I
dsn
I
dsp
V
out
V
DD
V
in

30. MOS equations Slide 30
pMOS Operation
Cutoff Linear Saturated
V
gsp> V
tp V
gsp< V
tp
V
dsp> V
gsp–V
tp
V
gsp< V
tp
V
dsp< V
gsp–V
tpI
dsn
I
dsp
V
out
V
DD
V
in

31. MOS equations Slide 31
pMOS Operation
Cutoff Linear Saturated
V
gsp> V
tp V
gsp< V
tp
V
dsp> V
gsp–V
tp
V
gsp< V
tp
V
dsp< V
gsp–V
tpI
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in-V
DD
V
dsp
= V
out-V
DD
V
tp
< 0

32. pMOS Operation
Cutoff Linear Saturated
V
gsp> V
tp
V
in> V
DD+ V
tp
V
gsp< V
tp
V
in< V
DD+ V
tp
V
dsp> V
gsp–V
tp
V
out> V
in-V
tp
V
gsp< V
tp
V
in< V
DD+ V
tp
V
dsp< V
gsp–V
tp
V
out< V
in-V
tpI
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in-V
DD
V
dsp
= V
out-V
DD
V
tp
< 0

33. I-V Characteristics
Make pMOS is wider than nMOS such that b
n=
b
pV
gsn5
V
gsn4
V
gsn3
V
gsn2
V
gsn1
V
gsp5
V
gsp4
V
gsp3
V
gsp2
V
gsp1
V
DD
-V
DD
V
dsn
-V
dsp
-I
dsp
I
dsn
0

34. Current vs. V
out, V
inV
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD

35. Load Line AnalysisV
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
For a given V
in:
•Plot I
dsn, I
dspvs. V
out
•V
outmust be where |currents| are equal inI
dsn
I
dsp
V
out
V
DD
V
in

36. MOS equations Slide 36
Load Line AnalysisV
in0
V
in0
I
dsn
, |I
dsp
|
V
out
V
DD
V
in= 0

37. Load Line AnalysisV
in1
V
in1I
dsn
, |I
dsp
|
V
out
V
DD
V
in= 0.2V
DD

38. MOS equations Slide 38
Load Line AnalysisV
in2
V
in2
I
dsn
, |I
dsp
|
V
out
V
DD
V
in= 0.4V
DD

39. Load Line AnalysisV
in3
V
in3
I
dsn
, |I
dsp
|
V
out
V
DD
V
in= 0.6V
DD

40. Load Line AnalysisV
in4
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
V
in= 0.8V
DD

41. Load Line AnalysisV
in5
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD
V
in= V
DD

42. Load Line SummaryV
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
I
dsn
, |I
dsp
|
V
out
V
DD

43. DC Transfer Curve
Transcribe points onto V
invs. V
outplotV
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
in1
V
in2
V
in3
V
in4
V
out
V
DD C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp

44. Operating Regions
Revisit transistor operating regionsC
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
Region nMOS pMOS
A Cutoff Linear
B SaturationLinear
C SaturationSaturation
D Linear Saturation
E Linear Cutoff

45. Beta Ratio
If b
p/ b
n1, switching point will move from
V
DD/2
Called skewedgate
Other gates: collapse into equivalent inverterV
out
0
V
in
V
DD
V
DD
0.5
1
2
10
p
n
b
b

0.1
p
n
b
b


46. Noise Margins
How much noise can a gate input see before it
does not recognize the input?Indeterminate
Region
NM
L
NM
H
Input CharacteristicsOutput Characteristics
V
OH
V
DD
V
OL
GND
V
IH
V
IL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range

47. Logic Levels
To maximize noise margins, select logic levels at V
DD
V
in
V
out
V
DD
b
p
/b
n
> 1
V
in
V
out
0

48. Logic Levels
To maximize noise margins, select logic levels at
•unity gain point of DC transfer characteristicV
DD
V
in
V
out
V
OH
V
DD
V
OL
V
IL
V
IH
V
tn
Unity Gain Points
Slope = -1
V
DD
-
|V
tp
|
b
p
/b
n
> 1
V
in
V
out
0

49. Transient Response
DC analysistells us V
outif V
inis constant
Transient analysistells us V
out(t) if V
in(t) changes
•Requires solving differential equations
Input is usually considered to be a step or ramp
•From 0 to V
DD or vice versa

50. Inverter Step Response
Ex: find step response of inverter driving load
cap0
()
(
)
)
(
o
i
ut
n
out
V t t
t
V
t
V
d
d
t


 V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

51. Inverter Step Response
Ex: find step response of inverter driving load
cap0
0
()
()
()
()
ou
DDin
t
out
u t t V
d
d
t
tt
Vt
V
V
t



 V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

52. Inverter Step Response
Ex: find step response of inverter driving load
cap0
0
(
())
(
(
)
)
DD
Do
i
D
ot
n
ut
u
Vt
u t t V
V
d
d
t
t
V
V
t
t


 V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

53. Inverter Step Response
Ex: find step response of inverter driving load
cap0
0
()
()
()
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
tt
Vt
V
d
dt C
t
It



 0
()
DD tout
ou
ds
t DD t
n
It VV
VV V
V
tt

  


 V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

54. Inverter Step Response
Ex: find step response of inverter driving load
cap0
0
()
()
()
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
tt
Vt
V
d
dt C
t
It



  
0
2
2
0
2
)
)
(
()
(
DD DD t
DD
out
out
out out Dt
n
t
ds
D
I V
tt
V V V V
V V V V V
t
Vt
Vt
b
b



   


   
 V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

55. Inverter Step Response
Ex: find step response of inverter driving load
cap0
0
()
()
()
(
(
)
)
DD
DD
loa
d
ou
i
d
t
o
n
ut sn
V
V
u t t V
tt
Vt
V
d
dt C
t
It



  
0
2
2
0
2
)
)
(
()
(
DD DD t
DD
out
out
out out Dt
n
t
ds
D
I V
tt
V V V V
V V V V V
t
Vt
Vt
b
b



   


   
 V
out
(t)
V
in
(t)
t
0
t V
in
(t)
V
out
(t)
C
load
I
dsn
(t)

56. Delay Definitions
t
pdr: rising propagation delay
•From input to rising output crossing V
DD/2
t
pdf: falling propagation delay
•From input to falling output crossing V
DD/2
t
pd: average propagation delay
•t
pd= (t
pdr+ t
pdf)/2
t
r: rise time
•From output crossing 0.2 V
DDto 0.8 V
DD
t
f: fall time
•From output crossing 0.8 V
DDto 0.2 V
DD

57. Delay Definitions
t
cdr: rising contamination delay
•From input to rising output crossing V
DD/2
t
cdf: falling contamination delay
•From input to falling output crossing V
DD/2
t
cd: average contamination delay
•t
pd= (t
cdr+ t
cdf)/2

58. Simulated Inverter Delay
Solving differential equations by hand is too hard
SPICE simulator solves the equations
numerically
•Uses more accurate I-V models too!
But simulations take time to write (V)
0.0
0.5
1.0
1.5
2.0
t(s)
0.0 200p 400p 600p 800p 1n
t
pdf
= 66ps t
pdr
= 83ps
V
in
V
out

59. Delay Estimation
We would like to be able to easily estimate delay
•Not as accurate as simulation
•But easier to ask “What if?”
The step response usually looks like a 1
st
order
RC response with a decaying exponential.
Use RC delay models to estimate delay
•C = total capacitance on output node
•Use effective resistanceR
•So that t
pd= RC
Characterize transistors by finding their effective
R
•Depends on average current as gate switches

60. RC Delay Models
Use equivalent circuits for MOS transistors
•Ideal switch + capacitance and ON resistance
•Unit nMOS has resistance R, capacitance C
•Unit pMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to widthkg
s
d
g
s
d
kC
kC
kC
R/k
kg
s
d
g
s
d
kC
kC
kC
2R/k

61. Delay Components
Delay has two parts
•Parasitic delay
6 or 7 RC
Independent of load
•Effort delay
4h RC
Proportional to load capacitance

62. 7C
3C
3C
3
3
3
222
3C
2C2C
3C3C
Isolated
Contacted
Diffusion
Merged
Uncontacted
Diffusion
Shared
Contacted
Diffusion Diffusion Capacitance
we assumed contacted diffusion on every s / d.
Good layout minimizes diffusion area
Ex: NAND3 layout shares one diffusion contact
•Reduces output capacitance by 2C
•Merged uncontacted diffusion might help too