Synchronous COUNTER presentation eng.ppt

Eng

1. EE 8315:DIGITAL ELECTRONICS
GROUP NO 18
METHOD OF DIGITAL TO ANALOG
CONVERSION
CollegeofEngineeringandTechnology(CET)
Department OfElectricalAnd power
Engineering.

2. Group 18
Synchronous (Parallel) Counters 2
Synchronous (Parallel) Counters
Synchronous (parallel) counters: the flip-flops are
clocked at the same time by a common clock pulse.
We can design these counters using the sequential
logic design process.
Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).Present Next Flip-flop
state state inputs
A1A0A1
+
A0
+
TA1TA0
00 01 0 1
01 10 1 1
10 11 0 1
11 00 1 1
0100
1011

3. Group 18
Synchronous (Parallel) Counters 3
Synchronous (Parallel) Counters
Example: 2-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J,K inputs).Present Next Flip-flop
state state inputs
A1A0A1
+
A0
+
TA1TA0
00 01 0 1
01 10 1 1
10 11 0 1
11 00 1 1
TA
1= A
0
TA
0= 1
1
K
J
K
J
A
1A
0
CC
CLK
Q
Q'
Q
Q'
Q
Q'

4. Group 18
Synchronous (Parallel) Counters 4
Synchronous (Parallel) Counters
Example: 3-bit synchronous binary counter (using T
flip-flops, or JK flip-flops with identical J, K inputs).Present Next Flip-flop
state state inputs
A2A1A0A2
+
A1
+
A0
+
TA2TA1TA0
000 001 0 0 1
001 010 0 1 1
010 011 0 0 1
011 100 1 1 1
100 101 0 0 1
101 110 0 1 1
110 111 0 0 1
111 000 1 1 1
TA2= A1.A0
A2
A1
A0
1
1
TA1= A0 TA0= 1
A2
A1
A0
1
11
1
A2
A1
A0
11 1
1111
1

5. Group 18
Synchronous (Parallel) Counters 5
Synchronous (Parallel) Counters
Example: 3-bit synchronous binary counter (cont’d).
TA2= A1.A0 TA1= A0 TA0= 1
1
A
2
CP
A
1 A
0
K
Q
J K
Q
J K
Q
J

6. Group 18
Synchronous (Parallel) Counters 6
Synchronous (Parallel) Counters
Note that in a binary counter, the n
th
bit (shown
underlined) is always complemented whenever
011…11 100…00
or111…11 000…00
Hence, X
nis complemented whenever
X
n-1X
n-2... X
1X
0= 11…11.
As a result, if T flip-flops are used, then
TX
n= X
n-1 . X
n-2 .... .X
1 .X
0

7. Group 18
Synchronous (Parallel) Counters 7
Synchronous (Parallel) Counters
Example: 4-bit synchronous binary counter.
TA
3= A
2. A
1. A
0
TA
2= A
1. A
0
TA
1= A
0
TA
0= 1
1
K
J
K
J
A
1A
0
CC
CLK
Q
Q'
Q
Q'
Q
Q'
K
J
A
2
C
Q
Q'
K
J
A
3
C
Q
Q'
A
1.A
0 A
2.A
1.A
0

8. Group 18
Synchronous (Parallel) Counters 8
Synchronous (Parallel) Counters
Example: Synchronous decade/BCD counter.Clock pulse Q3Q2Q1Q0
Initially 0000
1 0001
2 0010
3 0011
4 0100
5 0101
6 0110
7 0111
8 1000
9 1001
10 (recycle)0000
T
0= 1
T
1= Q
3'.Q
0
T
2= Q
1.Q
0
T
3= Q
2.Q
1.Q
0+ Q
3.Q
0

9. Group 18
Synchronous (Parallel) Counters 9
Synchronous (Parallel) Counters
Example: Synchronous decade/BCD counter
(cont’d).
T
0= 1
T
1= Q
3'.Q
0
T
2= Q
1.Q
0
T
3= Q
2.Q
1.Q
0+ Q
3.Q
0
1
Q
1
Q
0
CLK
T
C
Q
Q'
Q
Q'
Q
2 Q
3T
C
Q
Q'
Q
Q'
T
C
Q
Q'
Q
Q'
T
C
Q
Q'
Q
Q'

10. Group 18
Up/Down Synchronous Counters 10
Up/Down Synchronous Counters
Up/down synchronous counter: a bidirectional
counter that is capable of counting either up or
down.
An input (control) line Up/Down(or simply Up)
specifies the direction of counting.
Up/Down= 1 Count upward
Up/Down= 0 Count downward

11. Group 18
Up/Down Synchronous Counters 11
Up/Down Synchronous Counters
Example: A 3-bit up/down synchronous binary
counter.Clock pulseUpQ2Q1Q0Down
0 000
1 001
2 010
3 011
4 100
5 101
6 110
7 111
TQ
0= 1
TQ
1= (Q
0.Up) + (Q
0'.Up' )
TQ
2= ( Q
0.Q
1.Up )+ (Q
0'. Q
1'. Up' )
Up counter
TQ
0= 1
TQ
1= Q
0
TQ
2= Q
0.Q
1
Down counter
TQ
0= 1
TQ
1= Q
0’
TQ
2= Q
0’.Q
1’

12. group 18
Up/Down Synchronous Counters 12
Up/Down Synchronous Counters
Example: A 3-bit up/down synchronous binary
counter (cont’d).
TQ
0= 1
TQ
1= (Q
0.Up) + (Q
0'.Up' )
TQ
2= ( Q
0.Q
1.Up )+ (Q
0'. Q
1'. Up' )
1
Q
1Q
0
CLK
T
C
Q
Q'
Q
Q'
T
C
Q
Q'
Q
Q'
T
C
Q
Q'
Q
Q'
Up
Q
2

13. group 18
Designing Synchronous Counters 13
Designing Synchronous Counters
Example: A 3-bit Gray code
counter (using JK flip-flops).
100
000
001
101
111
110
011
010Present Next Flip-flop
state state inputs
Q2Q1Q0Q2
+
Q1
+
Q0
+
JQ2KQ2JQ1KQ1JQ0KQ0
000 001 0 X 0 X 1 X
001 011 0 X 1 X X 0
010 110 1 X X 0 0 X
011 010 0 X X 0 X 1
100 000 X 1 0 X 0 X
101 100 X 0 0 X X 1
110 111 X 0 X 0 1 X
111 101 X 0 X 1 X 0

14. group 18
Designing Synchronous Counters 14
Designing Synchronous Counters
3-bit Gray code counter: flip-flop inputs.
0
1
00 01 11 10Q
2
Q
1Q
0
XXXX
1
JQ
2= Q
1.Q
0'
0
1
00 01 11 10Q
2
Q
1Q
0
XXXX
1
KQ
2= Q
1'.Q
0'
0
1
00 01 11 10Q
2
Q
1Q
0
XX
XX1
JQ
1= Q
2'.Q
0
0
1
00 01 11 10Q
2
Q
1Q
0
XX
XX
1
KQ
1= Q
2.Q
0
0
1
00 01 11 10Q
2
Q
1Q
0
XX
XX1
JQ
0= Q
2.Q
1+ Q
2'.Q
1'
= (Q
2Q
1)'
1
0
1
00 01 11 10Q
2
Q
1Q
0
XX
XX 1
1
KQ
0= Q
2.Q
1'+ Q
2'.Q
1
= Q
2Q
1

15. group 18
Designing Synchronous Counters 15
Designing Synchronous Counters
3-bit Gray code counter: logic diagram.
JQ
2= Q
1.Q
0'JQ
1= Q
2'.Q
0JQ
0= (Q
2Q
1)'
KQ
2= Q
1'.Q
0'KQ
1= Q
2.Q
0KQ
0= Q
2Q
1
Q
1Q
0
CLK
Q
2
J
C
Q
Q'K
J
C
Q
Q'K
J
C
Q
Q'K
Q
2
'
Q
0
'
Q
1
'

16. The End………….