Thiet ke so Digital design zdsfasdfsadf.pptx

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1. TRƯỜNG ĐẠI HỌC BÁCH KHOA HÀ NỘI VIỆN ĐIỆN TỬ VIỄN THÔNG IC Design Lab Introduction

2. 1. Introduction Contents 2. Design Project 3. Simulation 4. Synthesize the design 1. Introduction

3. 1. Introduction Modelsim Quartus

4. 1. Introduction 1.1 Modelsim ModelSim is a verification and simulation tool for VHDL, Verilog, SystemVerilog , and mixed-language designs. Software : ModelSim -Altera 6.6d Starter Edition References : Introduction to Simulation of Verilog Designs Using ModelSim Graphical Waveform Editor (Altera). ModelSim Tutorial (Mentor Graphics). http://www.altera.com

5. 1. Introduction 1.2 Quartus Quartus . Software : Quartus II 11.1 Web Edition References : Quartus Tutorial . http://www.altera.com

6. 1. Introduction Contents 2. Design Project 3. Simulation 4. Synthesize the design 2. Design Project

7. 2. Design Project Simple example : f(x 1 , x 2 , x 3 ) = x 1 x 2 + x 2 x 3 + x 3 x 1 Verilog code : m odule majority(x1, x2 ,x3 ,f); input x1, x2, x3; output f; assign f = (x1&x2)|(x2&x3)|(x3&x1); e ndmodule ;

8. 2. Design Project Open the ModelSim simulator. In the displayed window select File > New > Project

9. 2. Design Project A Create Project pop-up box will appear… 1.Enter the name of the project Choose Project Location

10. 2. Design Project Create new file… 1 2 3

11. 2. Design Project Double click Text Editor

12. 2. Design Project Or add existing file…

13. 2. Design Project After completed coding, select Compile > Compile all Compile of majority.v was successfull

14. 1. Introduction Contents 2. Design Project 3. Simulation 4. Synthesize the design 3. Simulation 3. Simulation 3. Simulation

15. 3 . Simulation 3.1. Simulate without testbench 3.2. Simulate with testbench

16. 3. Simulation 3.1 . Simulate without testbench Select Simulate > Start simulation…, Start Simulation window will appear…

17. 3. Simulation Simulation window…

18. 3. Simulation Create waveforms for Simulation…

19. 3. Simulation Modify waveforms for Simulation…

20. 3. Simulation Waveform window…

21. 3. Simulation Waveform window…

22. 3. Simulation With output signal…

23. 3. Simulation Simulate…Select Run all

24. 3. Simulation Result… To stop simulation, slect Simulate -> End simulation

25. 3. Simulation 3.2 . Simulate with testbench Create testbench file to project

26. 3. Simulation After completed coding, select Compile > Compile all

27. 3. Simulation Add signal to waveform…

28. 3. Simulation Add signal to waveform…

29. 3. Simulation Simulate…

30. 3. Simulation Zoom in, zoom out …

31. 1. Introduction Contents 2. Design Project 3. Simulation 4. Synthesize the design 4. Synthesize the design

32. 4 . Synthesize the design Open the Quartus . In the displayed window select File > New Project Wizard…

33. 4. Synthesize the design A New Project Wizard box will appear… www.themegallery.com 1. Directory 2 . Name

34. 4. Synthesize the design Family & Device Settings will appear …

35. 4. Synthesize the design

36. 4. Synthesize the design Entity will appear …

37. 4. Synthesize the design Text editor code … Ctrl + S … save…

38. 4. Synthesize the design Or add file …

39. 4. Synthesize the design After coding , select Processing > Start Complation …

40. 4. Synthesize the design RTL viewer select Tool > Netlist Viewers > RTL Viewer …

41. 4. Synthesize the design Assign select Assignments > Pin Planner … Build

42. 4. Synthesize the design After Assign, select Toll > Programmer …

43. Thank You !