timing diagram-1.pptxMechatronics engineering Guindy

Mechatronics engineering Guindy

1. Timing Diagram is a graphical representation . It represents the execution time taken by each instruction in a graphical format . The execution time is represented in T-states. Instruction Cycle: The time required to execute an instruction is called instruction cycle. Machine Cycle: The time required to access the memory or input/output devices is called machine cycle. The 8085 microprocessor has 5 (seven) basic machine cycles. They are Opcode fetch cycle ( 4T or 6T) 1 st machine cycle Cycle in which the processor decides the nature of instruction to be executed Memory read cycle (3 T) Memory write cycle (3 T) I/O read cycle (3 T) I/O write cycle (3 T) Interrupt Acknowledge cycle(6T or 12T) Bus idle cycle T-State : The machine cycle and instruction cycle takes multiple clock periods. A portion of an operation carried out in one system clock period is called as T-state .

2. Each instruction of the 8085 processor consists of one to five machine cycles, i.e., when the 8085 processor executes an instruction, it will execute some of the machine cycles in a specific order. The processor takes a definite time to execute the machine cycles. The time taken by the processor to execute a machine cycle is expressed in T-states . One T-state is equal to the time period of the internal clock signal of the processor. The T-state starts at the falling edge of a clock . In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.

3. SJCET Machine cycle 2 Machine cycle 5 Instruction cycle Machine cycle1 T – State 1 T – State 2 T – State 3 T – State 6

4. Clock Signal The 8085 divides the clock frequency provided at x1 and x2 inputs by 2 which is called operating frequency. Rise time and fall time 8085 is connected to the crystal frequency 6.144MHz Crystal frequency is divided internally by 2 – operating frequency is 3.072MHz – time period is 0.325µsec One T-state is equal to the time period of the internal clock signal of the processor. SJCET T-State 1 Clock cycle

5. Single Signal Single signal status is represented by a line. It may have status either logic 0 or logic 1 or tri-state SJCET Logic 0 Logic 1 Tri state

6. Group of signals Group of signals is also called a bus. Eg: Address bus, data bus SJCET State changes Valid state Tri state

7. CONTROL SIGNALS

8. Timing diagram of various signals Address latch enable: Address latch enable is an active high signal. (i.e.) the latch becomes enabled when the signal is high. It is activated during the beginning of T1 state of each machine cycle and it remains active in the T1state. But in case of bus idle machine cycle it is not activated.

9. Data Bus (D0-D7): While dealing with data bus, two types of data flow are possible. The data can be transferred from memory to microprocessor and vice versa. This process occurs during the T2 and T3 states. There are 2 cycles. Read machine cycle the data will appear during the later part of T2 state, while in Write machine cycle the data will appear on the beginning of T2 state. for reading a data from memory or I/O device, first we need to select the required device. After selecting the device, the required data to be read or written is taken from the selected location and placed on data bus. A certain amount of time is required to perform this action. This time is called “access time". write machine cycle the access time is 0. This is because the data to be written is present on the registers of microprocessor and so it can put the data directly to data bus without any time delay.

10. Lower byte address (A0-A7): The lower byte of address is available on the time multiplexed address/date bus during the T1 state of machine cycle, except the bus idle machine cycle.

11. Higher byte addresses (A8-A15): The higher byte addresses (A8-A15) is available for T1, T2 and T3 states of each machine cycle, except the bus idle machine cycle.

12. IO/M’, S0, S1: IO/M’, S0, S1 are the status signals of the microprocessor. These status signals decide the type of machine cycle is to be executed. They remain activated from the beginning T1 state of a particular machine cycle and remains till the end of that machine cycle.

13. RD’ and WR’: These 2 signals RD’ and WR’ decides the direction of the data transfer. RD’ is Active: When RD’ goes active, the data is transmitted from memory, I/O device or any other peripherals to the microprocessor. WR’ is active: When WR’ goes active, the data is transmitted from microprocessor to the memory or any other peripheral devices. In 8085 microprocessor either RD’ goes high or WR’ goes high. Both cannot take place at same time. The data transfer both RD’ and WR’ takes place during T2 and T3 states of machine cycle. So these signals are activated during the T2 and T3 states.

14. Machine Cycle Memory Write Machine cycle is used for sending data from the registers of the microprocessor to the memory or any other I/O devices. Simple example for such an instruction is  MOV M, A When the above instruction is executed the contents of the accumulator is moved to the specified memory location. Two machine cycles Opcode fetch cycle Second to transfer the contents of memory to the accumulator.

15. T1 State: This is the Opcode fetch cycle where the microprocessor places the 16 bit address on the higher order address bus (A8 - A15) and lower order address and data multiplexed bus (AD0 - AD7). The ALE goes high to latch the AD0 - AD7 bus and during the middle of T1 state it goes low, so that the complete 16 bit address is available. the microprocessor recognize about what operation should be performed? The microprocessor can recognize it using the status signal IO/M’, S0 and S1. For memory write cycle the values of status signals should be IO/M’= 0 S1=0 S0=1 This status information is always maintained throughout the machine cycle. T2 State: At the beginning of this state WR’ goes low (as it is a memory write cycle). Whereas in read cycle the RD’ goes low to enable memory. During this state the contents of the register is placed on the Data bus. T3 State: The data which was placed on the data bus in the previous state is now transferred to the specific memory location. In the middle of this state the WR’ goes high and disables the memory. Thus the data is transferred from the accumulator to specific memory location. This is the memory write machine cycle.

16. I/O Write Machine Cycle Memory read and I/O read operations are similar to each other. Memory write and I/O write operations are similar to each other. Example of I/O write machine cycle is OUT 23H When the above instruction is executed, the data is transferred from accumulator to the specified location of the output device (in this case it is 23H). The microprocessor recognizes the I/O write machine cycle from the status signals IO/M’=1, S0=1, S1=0. In the I/O write machine cycle, external latching using ALE is not necessary. This is because in this machine cycle, the address is duplicated and is available on the address bus till the end of the machine cycle.

17. Memory Read Machine Cycle of 8085 The memory read machine cycle is executed by the processor to read a data byte from memory . The processor takes 3T states to execute this cycle . The instructions which have more than one byte word size will use the machine cycle after the opcode fetch machine cycle.

18. Op-code fetch machine cycle of 8085 Each instruction of the processor has one byte opcode . The opcodes are stored in memory. So, the processor executes the opcode fetch machine cycle to fetch the opcode from memory. Hence, every instruction starts with opcode fetch machine cycle. The time taken by the processor to execute the opcode fetch cycle is 4T. In this time, the first, 3 T-states are used for fetching the opcode from memory and the remaining T-states are used for internal operations by the processor.