Timing diagram of microprocessor 8085

Total slides: 39
Introduction to the Timing Diagram
Machine Cycles
Machine Cycles of Microprocessor 8085
Opcode Fetch Machine Cycle
Memory Read Machine Cycle
Memory Write Machine Cycle
IO Read Machine Cycle
IO Write Machine Cycle
Examples

1. Timing Diagram of Microprocessor 8085
Dr. Nilesh Bhaskarrao Bahadure
https://www.sites.google.com/site/nileshbbahadure/home
July 26, 2021
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2. Overview
1
Introduction to the Timing Diagram
Introduction to the Timing Diagram
Machine Cycles
Machine Cycles of Microprocessor 8085
Opcode Fetch Machine Cycle
Memory Read Machine Cycle
Memory Write Machine Cycle
IO Read Machine Cycle
IO Write Machine Cycle
2
Group-I One Machine Cycle with 4 T - States
3
Group-II One Machine Cycle with 6 T - States
4
Group-III Two Machine Cycle Instructions
Exceptions of the Group-III
5
Group-IV Three Machine Cycle Instructions
6
Group-V JMP Instruction
Conditional Jump Instruction
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3. Overview
7
Group-VI RET Instruction
Conditional RET Instruction
8
Group-VII CALL Instruction
Conditional CALL Instruction
9
Group-VIII LDA STA LHLD SHLD XTHL Instruction
10
Examples
Example-I MVI B, 43
Example-II INR M
Example-III IN C0
Example-IV STA
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4. Introduction to the Timing Diagram
Timing Diagram is a graphical representation of the instruction execution
in steps with respect to the time (clock signal). It represents the execution
time taken by each instruction in a graphical format. The execution time
is represented in T-states. The dierent types of cycles used in the timing
diagram representation are as follows:
Instruction Cycle:
Instruction cycle is dened as the time required completing the execution
of an instruction. The 8085Pinstruction cycle consists of one to ve
m/c cycles or one to ve operations.
Machine Cycle:Machine cycle is dened as the time required completing the operation of
accessing memory or input / output. In 8085P, m/c cycle may consists
of three to six timing state (T - state)
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5. Introduction to the Timing Diagram...
T-State:T State is dened as one subdivision of the operation performed in one
clock period. These subdivisions are internal states synchronized with the
system clock.
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6. Machine Cycles
Machine CycleStatus SignalsControl Signals
IO=MS1S0RDWRINTA
Opcode Fetch011011Memory Read010011Memory Write001101IO Read110011IO Write101101INTR ACK111110Bus Idle000111Main Slide
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7. Machine Cycles of Microprocessor 8085
Opcode fetch cycle (4T/6T)Memory read cycle (3 T)Memory write cycle (3 T)I/O read cycle (3 T)I/O write cycle (3 T)Halt state machine cycleInterrupt acknowledge machine cycle
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8. Opcode Fetch Machine Cycle
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9. Memory Read Machine Cycle
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10. Memory Write Machine Cycle
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11. IO Read Machine Cycle
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12. IO Write Machine Cycle
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13. One Machine Cycle Instructions 4 T - States
InstructionInstructionInstruction
MOV Rd, RsXCHGADD RADC RSUB RSBB RRALRLCRRCRARSTCCMCCMAINR RDCR RANA RORA RXRA RDAAEIDISIMRIMNOPCMP R
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14. One Machine Cycle Instructions 6 T - States
InstructionInstruction
INX RpDCX RpSPHLPCHL
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15. Two Machine Cycle Instructions
Instruction Machine
Cycle 1
Machine
Cycle 2
MVI Rd, DATAFRMOV R,MFRMOV M,RFWADI DATAFRACI DATAFRSUI DATAFRSBI DATAFRANI DATAFR
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16. Two Machine Cycle Instructions...
Instruction Machine
Cycle 1
Machine
Cycle 2
ORI DATAFRXRI DATAFRCPI DATAFRADD MFRADC MFRSUB MFRSBB MFRANA MFR
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17. Two Machine Cycle Instructions...
Instruction Machine
Cycle 1
Machine
Cycle 2
ORA MFRXRA MFRCMP M MFRLDAX RpFRSTAX RpFW
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18. Exceptions of the Group-III
Instruction Instructions
INR MDCR MMVI M, DATAIN 8-BIT PORT ADDRESSOUT 8-BIT PORT ADDRESS
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19. Three Machine Cycle Instructions
Instruction m/c Cycle 1m/c Cycle 2m/c Cycle 3
LXI Rp, DATAFRRINR MFRWDCR MFRWMVI M, DATAFRWIN 8- bit Port AddressFRIOUT 8- bit Port AddressFROPUSH RpSWWPOP RpFRRRSTnSWWDAD RpFBB
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20. Conditional & Unconditional Jump Instructions
Instruction m/c Cycle 1m/c Cycle 2m/c Cycle 3
JMP ADDRFRR
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21. Conditional Jump Instructions
Conditional Branching
Instruction Condition not
Satised
Condition Satis-
ed
JC ADDRF RF R RJNC ADDRF RF R RJZ ADDRF RF R RJNZ ADDRF RF R RJP ADDRF RF R RJM ADDRF RF R RJPE ADDRF RF R RJPO ADDRF RF R R
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22. Conditional & Unconditional RET Instructions
Instruction m/c Cycle 1m/c Cycle 2m/c Cycle 3
RETFRR
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23. Conditional RET Instructions
Conditional Branching
Instruction Condition not
Satised
Condition Satis-
ed
RCSS R RRNCSS R RRZSS R RRNZSS R RRPSS R RRMSS R RRPESS R RRPOSS R R
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24. Conditional & Unconditional CALL Instructions
Instructionm/c Cycle
1
m/c Cycle
2
m/c Cycle
3
m/c Cycle
4
m/c Cycle
5
CALL
ADDR
SRRWW
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25. Conditional CALL Instructions
Conditional Branching
Instruction Condition not
Satised
Condition Satised
CC ADDRS
R
S
RRWW
CNC ADDRS
R
S
RRWW
CZ ADDRS
R
S
RRWW
CNZ ADDRS
R
S
RRWW
CP ADDRS
R
S
RRWW
CM ADDRS
R
S
RRWW
CPE ADDRS
R
S
RRWW
CPO ADDRS
R
S
RRWWMain Slide
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26. LDA STA LHLD SHLD XTHL Instruction
Instruction Machine Cycles
LDA ADDRF
RRR
STA ADDRF
RRW
LHLD ADDRF
RRRR
SHLD ADDRF
RRWW
XTHLF
RRWWMain Slide
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27. Draw timing diagram for MVI B, 43
Example Draw timing diagram for MVI B, 43H. Assume that instruction is located
at memory location 2000h and the opcode of MVI B, data is 06h
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28. Draw timing diagram for MVI B, 43
Solution
Address Mnemonics Opcode/Data
2000hMVI B, 43h06h2001h43h
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29. Draw timing diagram for MVI B, 43
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30. Draw timing diagram for INR M
Example Draw timing diagram for the instruction INR M, which are located at
memory location address 4105. Assume that the opcode of INR M is 34h,
also assume that HL = 4250 and the contents of memory location 4250h
is 12h.
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31. Draw timing diagram for INR M
Solution
Address Mnemonics Opcode/Data
4105hINR M34h
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32. Draw timing diagram for INR M
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33. Draw timing diagram for IN C0
Example Draw the timing diagram for the instruction IN C0h with the following
information
4125h DBh (Opcode of IN instruction)4126h C0h
Assume that the contents of the port address C0h is 5Eh
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34. Draw timing diagram for IN C0
Solution
Address Mnemonics Opcode/Data
4125hIN C0hDBh4126hC0h
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35. Draw timing diagram for IN C0
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36. Draw timing diagram for STA 526Ah
Example Draw the timing diagram for the STA 526A instruction, assume that the
opcode of STA is 32h and it is fetched from the memory location address
41FFh.
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37. Draw timing diagram for STA 526Ah
Solution
Address Mnemonics Opcode/Data
41FFhSTA 526Ah32h4200h6Ah4201h52h
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38. Draw timing diagram for STA 526Ah
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39. Thank you
Please send your feedback at [email protected]
For more details and updates kindly visit
https://sites.google.com/site/nileshbbahadure/home
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