TPP-INTRODUCTION, EVOLUTION, FABRICATION.pptx

VLSI EVOLUTION

1. MOSFET FABRICATION AND SCALING Ms. Tejal Page VLSI Very Large Scale Integration

2. Evolution of vlsi 1947: First point contact transistor (3 terminal devices) Shockley, Bardeen and Brattain at Bell Labs 1958: First integrated circuit Built by Jack Kilby (Nobel Laureate) at Texas Instruments Robert Noyce (Fairchild) is also considered as a co-inventor

3. FIRST TRANSISTIOR

4. BEFORE TRANSISTOR……VACUUM TUBES ENIAC Vacuum Tubes (1946 ) Electronic Numerical Integrator And Computer was amongst the earliest electronic general-purpose computers made . ENIAC lost one vacuum tube roughly every day or two. With almost 18,000 tubes, locating and replacing the failed one was challenging.

5. INTEGRATED CIRCUITS INTEGRATED CIRCUITS is a set of electronic circuits on a small flat piece of semiconductor material.

6. a. Evolution of minimum feature size in IC b. Level of integration versus time Feature Size???

7. Modern transistors are few microns wide and approximately 0.1 micron or less in length Human hair is 80-90 microns in diameter

8. MOORE’S LAW No of transistors double after every 18 months “The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years.” Gordon Earle Moore C o-founder and Chairman Emeritus of Intel Corporation

9. qUESTIONS Why semiconductor used in VLSI? Why do we need VLSI ?, Advantages of VLSI Disadvantages of VLSI Why MOSFET used in VLSI?

10. Fabrication process Nmos , pmos and cmos

11. mosfets Four terminal device: gate, source, drain, body Gate – oxide – body stack looks like a capacitor Gate and body are conductors (body is also called the substrate) SiO 2 (oxide) is a “good” insulator (separates the gate from the body Called metal–oxide–semiconductor (MOS) capacitor, even though gate is mostly made of poly-crystalline silicon ( polysilicon ) NMOS PMOS

12. cmos NMOS PMOS

13. NMOS FABRICATION

14. STEP- 1 Processing is carried on single crystal silicon of high purity on which required P impurities are introduced as crystal is grown. Such wafers are about 75 to 150 mm in diameter and 0.4 mm thick and they are doped with say boron to impurity concentration of 10 to power 15/cm3 to 10 to the power 16 /cm3

15. STEP-2 oxidation A layer of silicon di oxide (SiO2) typically 1 micrometer  thick is grown all over the surface of the wafer to protect the surface, acts as a barrier to the dopant during processing, and provide a Generally  insulating substrate  on to which other layers may be deposited and patterned.

16. STEP- 3 The surface is now covered with the photo resist which is deposited onto the wafer and spun to an even distribution of the required thickness.

17. STEP - 4 photlithography The photo resist layer is then exposed to ultraviolet light through masking which  defines those regions into which diffusion is to take place together with transistor channels. Assume, for example , that those areas exposed to uv radiations are polymerized (hardened), but that the areas required for diffusion are shielded by the mask and remain unaffected.

18. STEP- 5 etching These areas are subsequently readily etched away together with the underlying silicon di oxide so that the wafer surface is exposed in the window defined by the mask.

19. STEP-6 oxidation The remaining photo resist is removed and a thin layer of SiO2 (0.1 micro m typical) is grown over the entire chip surface and then poly silicon is deposited on the top of this to form the gate structure. The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition (CVD). In the fabrication of fine pattern devices, precise control of thickness, impurity concentration, and resistivity is necessary

20. STEP- 7 polysilicon deposition Further photo resist coating and masking allows the poly silicon to be patterned and then the thin oxide is removed to expose areas into which n-type impurities are to be diffused to form the source and drain. Diffusion is achieved by heating the wafer to a high temperature and passing a gas containing the desired n-type impurity. Note: The poly silicon with underlying thin oxide and the thick oxide acts as mask during diffusion the process is self aligning.

21. STEP 8 Diffusion/ Ion Implantation

22. STEP- 9 Thick oxide  (SiO2) is grown over all again and is then masked with photo resist and etched to expose selected areas of the poly silicon gate and the drain and source areas where connections are to be made. (contacts cut)

23. STEP-10 The whole chip then has metal ( aluminium ) deposited over its surface to a thickness typically of 1 micro m. This metal layer is then masked and etched to form the required interconnection pattern.

24. Why NMOS preferred over PMOS ? Why CMOS most commonly used? QUESTIONS