The final project report of "Two stage op amp design on cadence"
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University at Buffalo
Department of Electrical Engineering
EE491/591 Analog Circuit
Two Stage Op-Amp Design on Cadence
& Mosek Optimization
Prepared by
Haowei Jiang
ID 5016 6365 [email protected]
Electrical Engineering
11 December 2015
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3114 Deer Lakes Dr.
Amherst, NY, USA
14228
11 December 2015
Haowei Jiang, Graduate student
Electrical Engineering
University at Buffalo
Buffalo, NY
14260
Dear Sir:
This report, entitled " Two Stage Op-Amp Design on Cadence & Mosek Optimization”, was prepared
as my Project Report for the University at Buffalo. This report is in fulfillment of the course
EE491/591 Analog Circuit. The purpose of this report is to demonstrate the basic method of two
stage Op-Amp design, simulation on Cadence and optimization using Mosek. It is a self-study
report.
An acknowledgment of any assistance you received. I hereby confirm that I have received no further
help other than what is mentioned above in writing this report. I also confirm this report has not
been previously submitted for academic credit at this or any other academic institution.
Sincerely yours
Haowei Jiang
5016 6365
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Contributions
This is a self-study project report not based on the experienced gained at my previous co-op project.
My tasks consisted of hand calculation of Op-Amp parameters, cadence schematic plot, DC & AC
analysis, modification based on specification, introduction of Mosek Optimization and simulation
on Matlab.
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Summary
The main purpose of the report is to show the basic methods for designing a two stage Op-Amp
based on Cadence, and demonstrates and DC schematic plot and AC analysis simulation.
It comes that the result is highly close but not perfectly to the required specification.
Besides, this report presents the geometry optimization concerning the input configuration on
Matlab. However, it is a rather time-consuming process the software goes into NO-response. It
should be worked well with less subjective constraints.
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List of Figures
Figure 1.1. Hand calculation Stage-1 Input. ............................................................................ 2
Figure 1.2. Hand calculation Stage-2 output & Gain &Power Dissipation. ............................ 3
Figure 3.1.1 DC operating point of all transistors (Vin,CM,min=1V). ................................... 6
Figure 3.1.2 DC operating point of all transistors (Vin,CM,max=2V). .................................. 7
Figure 3.2.2.1 Modified parameters of transistors in 2-Stage Op-amp. .................................. 9
Figure 3.2.2.2 Modified DC operating points of transistors in 2-Stage Op-amp
(Vin,CM,min=1V). ................................................................................................................... 10
Figure 3.2.2.3 Modified DC operating points of transistors in 2-Stage Op-amp
(Vin,CM,min=2V). ................................................................................................................... 10
Figure 3.2.3.1 Gain VS GBW VS PM plot. .......................................................................... 12
Figure 4.1.1 Two Stage Op-Amp Biasing Conditions. .......................................................... 15
Figure 4.1.2 Objective Function & Subjective Constraints. .................................................. 16
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List of Tables
Table 1.1. Hand Calculation design parameters of 2-Stage Op-amp. ..................................... 4
Introduction
This report presents the design of two-stage Op-Amp and TSMC025 simulation based on Cadence,
including hand calculations for SPICE level 1 model, design schematic, and simulation verification
which followed by specifications shown as below:
(a) Phase margin 60°
(b) AV > 7500 V/V= 77.5dB
(c) VDD = 3.3V
(d) VSS = 0 V
(e) GB = 10MHz
(f) SR > 10V/µV
(g) Vout Range = 0.4 to 2.9 V
(h) ICMR = 1 V to 2V
(i) Pdiss < 5mW
(j) CL = 10pF
The report also shows the optimization of Level 1 design based on Mosek
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1.0 Hand calculations for SPICE Level-1 model
We choose Lmin=250nm to keep the channel modulation parameter constant. Scanned version and
parameters table are shown as below:
(Assuming: Sn= (W/L)n, βn= Kn*Sn)
Fig 1.1 Hand calculation Stage-1 Input
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Fig 1.2 Hand calculation Stage-2 output & Gain &Power Dissipation
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Table 1.1 Hand Calculation design parameters of 2-Stage Op-amp
2.0 Design Schematic
As shown in Fig 2.1 below (based on hand calculation):
Fig 2.1 Two-stage Op-Amp design schematic
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3.0 Design Verification:
3.1 DC analysis:
We have to run DC analysis before AC analysis. Based on the hand calculation on Fig 1.1, the we
choose bias current I5=100μA, Vin,CM,min=1V Vin,CM,max=2V, then run the DC analysis to check
whether all transistors are in region 2, that is, saturation, and the DC operating point of each
transistors are shown in Fig 3.1.1 and Fig 3.1.2:
Fig 3.1.1 DC operating point of all transistors (Vin,CM,min=1V)
We could see that when Vin,CM,min=1V, each transistor is in saturation. Vds5 = 341.527mV > 100mV
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Fig 3.1.2 DC operating point of all transistors (Vin,CM,max=2V)
When Vin,CM,max=2V , all the transistors are in saturation too. Vds5 = 1.14499V > 100mV
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3.2 AC Analysis:
3.2.1 Manual calculation for gain:
We use Vin,CM,min=1V, then run DC analysis first:
Fig 3.2.1.1 gds ad gm in M2
Fig 3.2.1.2 gds ad gm in M4
Fig 3.2.1.3 gds ad gm in M6
Fig 3.2.1.4 gds ad gm in M7
Av1=gm2 / (gds2+gds4) = 584.732μ / (16.7393μ + 8.10513μ) = 23.54
Av2=gm6 / (gds6+gds7) = 5.56525m/ (461.164μ + 588.948 μ) = 5.3
Total gain = Av1 * Av2 = 124.726, close to hand calculation result
Then we use Vin,CM,max=2V, and run DC analysis again:
Fig 3.2.1.5 gds ad gm in M2
Fig 3.2.1.6 gds ad gm in M4
Fig 3.2.1.7 gds ad gm in M6
Fig 3.2.1.8 gds ad gm in M7
Av1=gm2 / (gds2+gds4) = 783.492μ / (26.0794μ + 11.3768μ) = 20.91
Av2=gm6 / (gds6+gds7) = 5.56565m / (462.618μ + 589.157μ) = 5.3
Total gain = Av1 * Av2 = 110.8, close to hand calculation result
The Gains are Too low! So we have to modify the model parameters in some of the transistors
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3.2.2 Modification:
We should follow this table to change the parameters in transistors to meet requirements.
Fig 3.2.2.1 Modified parameters of transistors in 2-Stage Op-amp
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Fig 3.2.2.2 Modified DC operating points of transistors in 2-Stage Op-amp (Vin,CM,min=1V)
Fig 3.2.2.3 Modified DC operating points of transistors in 2-Stage Op-amp (Vin,CM,max=2V)
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Follow the method in 3.2.1, so the Gain calculation: (Vin,CM,min=1V)
clear;
clc;
3.2.3 ADE Analysis & Discussion:
Gain & phase: Result Direct plot AC magnitude & phase
Power: output save all choose input all run result browser dc-op dc
It appears that the gain we calculated above is still not big enough.
To ensure the GBW, we have already set Cc to min that is: Cc >= 0.22CL=2.2pF, we take Cc =
2.3pF.
To ensure the SR >10e6, in this case, I5 = 22.4005e-6 (close to minimum value!), so the
SR=I5/Cc, close to 10e6.
Power dissipation= 6.8406e-05 < 5mW
However, the gain is not qualified.
So, this simulation still needs to be modified and be tested enough times to meet the required
specification.
AC response is shown as below, the final plot should be like
Fig 3.2.3.1 Gain VS GBW VS PM plot
We could see that the gain is 75dB close to 20*log(7500)=77dB,where the GBW is 8.8MHz close to
required 10 MHz, and phase margin is 66 degree close to 60 degree.
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4.0 Mosek Optimization:
Here we use geometry optimization method where we apply the mskgpopt function in Matlab.
There are three input matrix variables in this function: A, c, map. Each row of A and c describes
one term, that is, each row of A represents the factors of unknowns, each row of c means the
coefficient of each term and map indicates he vector map indicated whether a term belongs to the
objective or to a constraint. If mapk equals zero, the kth term belongs to the objective function,
otherwise it belongs to the mapkth constraint.
If the A matrix size is m x n, that means there are m number of terms covered in functions and
constraints; n number of unknowns.
Example code:
(Please infer the code from Appendix)
We could derive that there are 26 terms and 10 unknowns, so the
Fig 4.1.2 Objective Function & Subjective Constraints
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4.2 Result:
(Please infer the code from Appendix)
It took quite a long time to calculate that the Matlab is always in BUSY status. And my software
showed no response.
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Conclusion:
In this report, we have shown how to design a two-stage Op-Amp with required specification with
Cadence.
First, you need to do the hand calculations to choose design parameters on each transistors based
on their relationships chipped inside the circuit.
Second, plot the schematics and input the calculated results in the Cadence, runs both DC and AC
analysis.
Last, one has to modified the parameters and simulate several times until it meets all of the
specifications.
Also, we represent a Geometry Optimization method based on MOSEK Matlab to gain a better
design. However, we only shows derivations of objective function, subjective constraints and the
codes but did not get a result since the calculation is too time-consuming.
It should be worked well with less subjective constraints.