Unit 3 (Complete) - 8086 Interrupt Structure.pdf

micro processors and microcontrollers

1. MICROPROCESSORS AND
MICROCONTROLLERS
Unit # 3
8086 Microprocessor
Interrupt Structure
DR. RAJ GAURAV MISHRA (NMIMS INDORE) - JAN 2025

3. Unit #Description Duration
3 8086 Interrupt Structure: Instruction, Hardware software
and program generated interrupts in 8086. Response to
interrupt, Interrupt vector Table, Interrupt acknowledge
machine cycle, 8259 PCI, EOI, and interfacing with
8086.
6 Lectures
Access Study Material

4. Interrupts in 8086 Microprocessor
•Aninterruptisaconditionthathaltsthemicroprocessortemporarilyto
workonadifferenttaskandthenreturnstoitsprevioustask.
•AninterruptisaneventorsignalthatrequeststheCPU’sattention.
•Thishaltallowsperipheraldevicestoaccessthemicroprocessor.
•Whenever an interrupt occurs, the processor completes the current
instruction and starts the implementation of anInterruptService
Routine(ISR) or Interrupt Handler.

5. Types of Interrupts in 8086 Microprocessor

6. Hardware Interrupts in 8086 Microprocessor
•Theseinterruptsaregeneratedbyexternalhardwaredevices(like
keyboards,timers,etc.)tosignalthemicroprocessorthatitneeds
attention.
•ThehardwareinterruptsareconnectedtotheInterruptRequestLines
(IR0toIR7).
•IR0toIR7(Pin#17to24):Theseareconnectedtoexternalhardware
devices.IR0isthehighestpriority,andIR7isthelowestpriority.These
interruptsaremaskable,meaningtheycanbedisabledifneeded.

7. Types of Hardware Interrupts in 8086 Microprocessor
•MaskableHardwareInterruptsare interruptsthatcanbedisabledor
"masked"bytheprocessorifneeded. In other words, the processor
has the capability to ignore or prevent the interrupt from interrupting
its current operations by using specific instructions or mechanisms.
TheInterruptFlag(IF)intheFlagsRegister is used to enable or
disable interrupts globally in the processor.
•Non-MaskableHardwareInterrupts(NMI)are a type of interruptthat
cannotbedisabled(masked)bytheprocessor.This is why they are
oftenusedforcriticalsystemeventsthat require immediate attention,
such as hardware failures or critical system errors. NMIs will always
interrupt the processor, regardless of whether interrupts are globally
enabled or disabled through the Interrupt Flag (IF).

8. Types of Hardware Interrupts in 8086 Microprocessor
TheINTR(InterruptRequest)isamaskableinterruptinthe8086
microprocessor.
IftheIFflagisset(IF=1),theprocessorwillrespondtoINTRrequests
(i.e.,itisenabled).
IftheIFflagiscleared(IF=0),theprocessorwillignoreincomingINTR
requests(i.e.,itisdisabled).

9. Internal Interrupts (Exceptions) in 8086 Microprocessor
•InternalInterrupts(alsoknownasExceptions)areinterruptsthatare
generatedbythe8086microprocessoritselfduetoerrorsor
exceptionalconditionsthatoccurduringtheexecutionofinstructions.
•Unlike external interrupts (which come from peripheral devices),
internalinterruptsarisefromissueswithintheprocessor, such as
invalid instructions, errors in data handling, or other unexpected
conditions.

10. Types of Internal Interrupts (Exceptions) in 8086
Microprocessor
1.DivisionbyZero(Type0-DivideError): Division by zero during arithmetic
operation
2.Overflow(Type4-OverflowError): Arithmetic overflow (result exceeds
operand size)
3.InvalidOpcode(Type6-InvalidOpcodeFault): Encountering an invalid or
unrecognized opcode
4.SegmentNotPresent(Type11-SegmentNotPresentFault): Access to an
unavailable or non-existent memory segment
5.StackFault(Type12-StackFault): Stack overflow or underflow

11. Types of Internal Interrupts (Exceptions) in 8086
Microprocessor
6.GeneralProtectionFault(Type13-GeneralProtectionFault): Access violation or
protection violation in memory
7.PageFault(Type14-PageFault): Invalid memory page access (paging error)
8.FloatingPointError(Type16-FloatingPointError): Error in floating-point
operations (e.g., division by zero)
9.BoundsCheck(Type5-BoundsCheckException): Accessing memory outside
the defined bounds
10.ControlProtectionFault(Type9-ControlProtectionFault): Violating control
operations in protected modes

12. Software Interrupts in 8086 Microprocessor
Inthe8086microprocessor,SoftwareInterruptsareinterruptsthataregenerated
bysoftwareinstructionsratherthanexternalhardwareevents.
These interrupts are typically invoked by the program itself using theINT
instruction.
Softwareinterruptsallowprogramstointeractwiththeoperatingsystemor
executespecificsystemservicesorfunctions.
A software interrupt is initiated by the INT instruction in the assembly language.
The INT instruction causes the processor to stop executing the current program
and jump to a specific memory address (the interrupt vector).
This vector points to the interrupt service routine (ISR) that handles the interrupt.

13. Types of Software Interrupts in 8086 Microprocessor
Softwareinterruptsin8086arebroadlyclassifiedintotwocategories:
StandardSoftwareInterrupts(SystemCalls):These are predefined interrupts in
the 8086 microprocessor that are used for system services. The interrupt number
defines the type of service requested. Many of these interrupt numbers are used
for interacting with DOS services, like reading input from a user or printing output
to the screen.
User-definedSoftwareInterrupts:8086 microprocessor also allows programmers
to define their own custom software interrupts. These are useful for custom
system services, error handling, or for implementing special routines within user
programs.

14. Types of Software Interrupts in 8086 Microprocessor
ExamplesofStandardSoftwareInterrupts(SystemCalls):
INT21H DOS interrupt for various system services, such as input/output, file handling, memory
allocation, etc.
INT10H Video services (e.g., setting video modes, clearing screen).
INT16H Keyboard services (e.g., reading key presses).
INT13H Disk services (e.g., reading from or writing to disk).
INT14H Serial communication services (e.g., sending and receiving data through serial ports).
ExamplesofCommonInterrupt21HServices(DOSInterrupts):
INT21H,AH=01H Read a character from standard input (keyboard).
INT21H,AH=02H Display a character on the screen.
INT21H,AH=09H Display a string of characters.
INT21H,AH=4CH Terminate a program and return to the operating system.

15. Types of Software Interrupts in 8086 Microprocessor
ExampleofUser-definedSoftwareInterrupts:
Aprogrammercanassignanyinterruptnumberbetween0and255toacustom
routine.
To define a user-defined interrupt, the programmer sets up the appropriate
interrupt vector in the Interrupt Vector Table (IVT) and writes the interrupt service
routine (ISR) for that interrupt number.
Forexample,aprogrammightcreateaninterruptwithnumberINT50Htohandle
aspecifictypeoferrorintheprogram.

16. Interrupt Service Routines (ISR) in 8086 Microprocessor
AnInterruptServiceRoutine(ISR) is a specialized subroutine in assembly or machine
language that is executed in response to an interrupt request.
TheISRisresponsibleforhandlingspecificeventstriggeredbyhardwareorsoftware
interruptsandensuringthatthesystemcontinuesfunctioningcorrectlyafterthe
interrupthasbeenprocessed.
AnISRisablockofcodethatisexecutedwhenaparticularinterruptoccurs.
When an interrupt occurs (either external or internal), the processor temporarily halts
the execution of the current program and jumps to a specific address in memory where
the ISR is located.ThisaddressisfoundintheInterruptVectorTable(IVT).
TheprocessorthenexecutestheISRtohandletheinterrupt.OncetheISRhasfinished
executing,controlisreturnedtothepointintheprogramwheretheinterruptoccurred.

17. Steps Involved in Handling an Interrupt via an ISR
1.InterruptOccurrence:An interrupt (either hardware or software)triggerstheINTR
(InterruptRequest)oranotherinterruptline.Iftheprocessor'sInterruptFlag(IF)is
enabled,itrespondstotheinterrupt.
2.ContextSaving:Theprocessorsavesthecurrentexecutioncontext(theprogram
counter,flags,andotherrelevantregisters)ontothestack.Thisallowsthe
processortorestorethecontextandresumenormaloperationaftertheISR
finishes.
3.InterruptAcknowledge(INTA):The processoracknowledgestheinterruptrequest
bysendinganInterruptAcknowledge(INTA)signal.Forhardwareinterrupts,thisis
asignalsenttotheinterruptingdevice,indicatingthattheinterruptisbeing
processed.
4.FetchISRAddress:TheprocessorretrievestheaddressoftheappropriateISRfrom
theInterruptVectorTable(IVT). TheIVTcontainstheaddressesofallISRsfor
differentinterrupts,indexedbytheinterruptnumber. The processor looks up the
corresponding entry in the IVT for the interrupt number that was triggered.

18. Steps Involved in Handling an Interrupt via an ISR
5.ExecuteISR:TheprocessorjumpstotheISR’saddressandbeginsexecutingthe
serviceroutine. The ISR is responsible for handling the interrupt and processing the
necessary tasks related to the interrupting event. For example:
•I/Ooperations:Reading data from an external device or sending data to it.
•Errorhandling:Resolving issues like memory access violations or hardware faults.
•Timers:Updating system time or managing periodic tasks.
6.RestoringContext:After the ISR completes,theprocessorrestoresthesaved
contextfromthestack.This includesrestoringtheProgramCounter(PC),flags,
andregisterstothevaluestheyhadbeforetheinterruptoccurred.
7.ReturntoNormalProgramExecution:Oncethecontextisrestored,theprocessor
returnstothemainprogramandcontinuesexecutionfromthepointwhereitwas
interrupted.TheIRET(InterruptReturn)instructionisusedtoreturnfromtheISR,
allowing the program to continue executing normally.

19. Steps Involved in Handling an Interrupt via an ISR

20. Example Code: Interrupt Service Routines (ISR) in 8086 Microprocessor

21. Interrupt Vector Table (IVT) in 8086 Microprocessor
TheInterruptVectorTable(IVT)isadatastructureusedinthe8086microprocessorto
storetheaddressesofinterruptserviceroutines(ISRs).
InterruptVectorTable(IVT)isacriticalcomponentinthe8086microprocessor’s
interrupthandlingmechanism.
ItenablestheprocessortoquicklyandefficientlylocatetheappropriateISRforeach
interrupttype,ensuringsmoothsystemoperationandresponsivenesstoexternaland
internalevents.

22. Interrupt Vector Table (IVT) in 8086 Microprocessor
LocationinMemory:The IVT starts at memory
address 0000H and occupies the first 1024 bytes
(256 interrupt vectors × 4 bytes per vector).
Structure:The IVT contains 256 entries (for
interrupts 0 to 255). Each entry in the table is 4
bytes:
2bytesfortheoffsetoftheISR.
2bytesforthesegmentoftheISR.

23. Interrupt Vector Table (IVT) in 8086 Microprocessor
Purpose:TheIVTstorestheaddresses
(segment:offset)ofInterruptServiceRoutines
(ISRs)forallinterrupts. It enables the processor to
quickly find the address of the ISR when an
interrupt occurs.
InterruptProcessing:When an interrupt occurs, the
processor uses the interrupt vector to locate the
corresponding ISR in the IVT. The processor then
jumps to the ISR, processes the interrupt, and
returns to the main program.

24. Interrupt Vector Table (IVT) in 8086 Microprocessor

25. Interrupt Vector Table (IVT) in 8086 Microprocessor

26. Interrupt Vector Table (IVT) in 8086 Microprocessor

27. Interrupt Acknowledge Machine Cycle
•CLK(Clock):The system clock signal
that synchronizes all operations.
•ALE(AddressLatchEnable): This
signal goes high in the first T-state of
a bus cycle to indicate a valid address
is being placed on AD0-AD7.
•LOCK'(BusLockSignal): If LOCK' = 0
(active low), the system bus is locked,
preventing other bus masters from
interrupting the processor during
critical operations.
•INTA'(InterruptAcknowledge): This is
an active-low signal indicating that
the 8086 is acknowledging an
interrupt. It is generated in response to
an INTR (maskable interrupt) request.
•AD0-AD7(MultiplexedAddress/Data
Bus): During the interrupt
acknowledgement cycle, the interrupt
vector number is placed on AD0-AD7.

28. Interrupt Acknowledge Machine Cycle
•The8086sendstwoINTA'pulsesto
acknowledgetheinterrupt.
•ThefirstINTA'cycleisfortheexternal
device to recognize the
acknowledgement.
•ThesecondINTA'cycleisforfetching
theinterruptvectornumber.
•The processor then fetches the
Interrupt Service Routine (ISR)
address from the Interrupt Vector
Table (IVT) and starts executing it.

29. Intel 8259A: Programmable Interrupt Controller
•TheProgrammableInterruptController(PIC)functionsasanoverallmanagerinan
interrupt-drivensystemenvironment.
•Itacceptsrequestsfromtheperipheralequipment,determineswhichofthe
incomingrequestsisofthehighestimportance(priority),ascertainswhetherthe
incomingrequesthasahigherpriorityvaluethanthelevelcurrentlybeingserviced
andissuesaninterrupttotheCPUbasedonthisdetermination.
•Eachperipheraldeviceorstructureusuallyhasaspecialprogramor,routinethatis
associatedwithitsspecificfunctionaloroperationalrequirements;thatisreferredto
asaserviceroutineorserviceprocedure.
•The 8259A PIC, after issuing an interrupt to the CPU, must somehow input
information (interrupt vector number) into the CPU that can point the program
counter to the service procedure associated with the requesting device.

30. Intel 8259A: Programmable Interrupt Controller
•Purpose:Manages multiple hardware interrupts for the 8086 microprocessor.
•InterruptHandling:Supports 8 interrupt requests (IR0–IR7), expandable up to 64
using cascading.
•PriorityMechanism:Provides priority-based interrupt handling and supports
nesting.
•OperatingModes:Supports fully nested, automatic rotation, and specific rotation
modes.
•CommunicationwithCPU:Uses Interrupt Command Words (ICWs) for initialization
and Operation Command Words (OCWs) for controlling interrupts.

31. Intel 8259A: Programmable Interrupt Controller
•TriggeringOptions:Works with edge-triggered and level-triggered interrupts.
•VectorAddressing:Supplies the interrupt vector number to the CPU for servicing
the interrupt.
•CascadingSupport:Allows connection of multiple 8259A PICs to handle more than
8 interrupts.
•Efficiency:Reduces CPU overhead by managing and prioritizing interrupts before
passing them to the processor.

32. Intel 8259A: Programmable Interrupt Controller
The8259AProgrammableInterruptController
(PIC) is an essential IC used in 8086
microprocessor-based systems to manage
hardware interrupts efficiently.
The8086hasonlyoneINTR(interruptrequest)
pin,the8259Aallowshandlinguptoeight
interruptsourcesbyprioritizingandqueuingthem.
Itisalsoknownasapriorityinterruptcontroller
andwasdesignedbyInteltoincreasethe
interrupthandlingabilityofthemicroprocessor.
An8259PICneverservicesaninterrupt;itsimply
forwardstheinterrupttotheprocessorforthe
executionofinterruptserviceroutine.

33. Intel 8259A: Programmable Interrupt Controller

34. Intel 8259A: Programmable Interrupt Controller

35. Intel 8259A: PIC Block Diagram

36. Intel 8259A: PIC Block Diagram
InterruptRequestRegister(IRR):
Stores pending interrupt requests
from IR0–IR7.
In-ServiceRegister(ISR):Keeps
track of active interrupts being
serviced.
PriorityResolver: Determines the
highest priority interrupt and sends
it to the CPU.
InterruptMaskRegister(IMR):
Masks/unmasks specific interrupt
lines as required.

37. Intel 8259A: PIC Block Diagram
Control Logic: Manages
communication between 8259A and
8086, including command words
(ICWs & OCWs).
DataBusBuffer: Interfaces with the
8086 data bus for transferring
control and interrupt vector
information.
Read/WriteControlLogic:Handles
data flow between CPU and 8259A
through RD, WR, CS, and A0
signals.

38. Intel 8259A: PIC Block Diagram
CascadeBuffer/Comparator:
Supports cascading multiple 8259A
chips for handling more than 8
interrupts.
InterruptOutput(INT&INTA̅):
Sends interrupt signals to 8086
(INT) and waits for acknowledgment
(INTA̅).

39. Intel 8259A Interfacing with 8086: PIC in Single Mode

40. Intel 8259A Interfacing with 8086: PIC in Cascade Mode

41. Intel 8259A: Programmable Interrupt Controller

42. Intel 8259A: PIC Operating Modes
FullyNestedMode:
•Default mode where highest priority (IR0–IR7) interrupt is serviced first.
•Lower priority interrupts wait until higher priority interrupts are completed.
AutomaticRotationMode
•After servicing an interrupt, its priority is shifted to the lowest.
•Ensures all interrupts get equal priority over time.
SpecificRotationMode
•Similar to automatic rotation but follows a user-defined priority order.
SpecialFullyNestedMode(SFNM)
•Used in cascaded 8259A configurations.
•Helps master 8259A handle interrupts from slave 8259A efficiently.

43. Intel 8259A: PIC Operating Modes
BufferedMode
•Used when 8259A operates in buffered systems (with bus drivers).
•Can work in Master or Slave mode based on SP/EN pin.
CascadeMode
•Supports multiple 8259A PICs (master-slave setup) for handling more than 8
interrupts.
•Uses CAS0–CAS2 lines for communication between master and slaves.
PolledMode
•Instead of using INT & INTA̅ signals, the CPU checks (polls) 8259A for pending
interrupts.
•Useful in systems where interrupts are not frequently used.

44. EOI (End of Interrupt) in 8259A
EOI(EndofInterrupt) is a command sent by the CPU to the 8259A PIC to inform
that the current interrupt service is complete.
Thisallowsthe8259AtoresettheIn-ServiceRegister(ISR)andacceptnew
interrupts.
PurposeofEOI:
•Informs 8259A that the CPU has completed servicing an interrupt.
•Allows new interrupts of the same or lower priority to be accepted.
EOIinNestedInterrupts:
•If multiple interrupts occur, EOI must be sent for each interrupt before lower-
priority ones can be serviced.
EOIinCascadedMode:
•When using multiple 8259A PICs, an EOI must be sent to both Master and Slave
PICs if the interrupt originated from the slave.

45. Types of EOI (End of Interrupt) commands in 8259A
SpecificEOI
•Used when the CPU explicitly specifies which interrupt to clear.
•Required in non-rotating priority modes.
Non-SpecificEOI
•Clears the highest priority interrupt that is currently being serviced.
•Used in nested and automatic rotation modes.
AutomaticEOI
•No explicit EOI command is needed from the CPU.
•The 8259A automatically clears ISR after the ISR routine is executed.
•Used in priority-based systems where interrupts are frequently occurring.

46. ICW (Initialization Command Words) in 8259A
PurposeofICW:
•Used for configuring the 8259A during initialization.
•Required after a system reset to define how the PIC operates.
•Total: 4 ICWs (ICW1–ICW4).
ICWFormat&Purpose:
1.ICW1: Selects basic operating mode (edge/level-triggered, single/cascaded
mode).
2.ICW2: Sets the interrupt vector address for interrupt handling.
3.ICW3: Used only in cascaded mode, defines master/slave connections.
4.ICW4: Enables special modes, such as automatic EOI or buffered mode.
WhenisICWUsed?
•During system boot-up or reset, when initializing 8259A.
•When changing the 8259A PIC configuration, such as switching from single to
cascade mode.

47. Initialization sequence of 8259A
ICWFormat&Purpose:
1.ICW1: Selects basic
operating mode (edge/level-
triggered, single/cascaded
mode).
2.ICW2: Sets the interrupt
vector address for interrupt
handling.
3.ICW3: Used only in cascaded
mode, defines master/slave
connections.
4.ICW4: Enables special
modes, such as automatic
EOI or buffered mode.

48. ICW (Initialization Command Words) in 8259A

49. ICW (Initialization Command Words) in 8259A

50. ICW (Initialization Command Words) in 8259A

51. OCW (Operation Command Words) in 8259A
PurposeofICW:
•Used for controlling interrupt operations after initialization.
•Total: 3 OCWs (OCW1–OCW3).
OCWFormat&Purpose:
1.OCW1: Enables or masks specific interrupts (IR0–IR7).
2.OCW2: Used for End of Interrupt (EOI), rotating priority, and specific interrupt
handling.
3.OCW3: Controls polling mode and checks the status of interrupts.
WhenisOCWUsed?
•When dynamically enabling/disabling interrupts.
•When sending EOI (End of Interrupt) commands.
•When switching to polling mode for software-based interrupt handling.

52. OCW (Operation Command Words) in 8259A

53. OCW (Operation Command Words) in 8259A

54. OCW (Operation Command Words) in 8259A

55. Polling in 8259A (Polled Mode)
8259AcanoperateinpollingmodewheretheCPUchecksitsstatusinsteadof
relyingonINT&INTA̅signals.
Inthismode,theCPUsendsapollcommandandreadstheInterruptRequest
Register(IRR)todeterminependinginterrupts.
NoneedforEOI(EndofInterrupt)commandssincetheCPUmanuallyclears
interrupts.

56. Topics Covered
•Interrupts in 8086, and their types,
•8086 Interrupt Structure,
•Interrupt Instructions,
•Hardware software and program generated interrupts in 8086,
•Response to interrupt,
•Interrupt Vector Table,
•Interrupt acknowledge machine cycle,
•8259A: Programmable Interrupt Controller,
•Operating Modes, EOI, and interfacing with 8086,
•ICWs and OCWs.

57. THANK YOU!
Dr. RAJ GAURAV MISHRA
Associate Professor – STME
[email protected]